Datasheet > APE3520VN4

APE3520VN4

更新时间： 2024-01-24 06:47:15

品牌	Logo	应用领域
富鼎先进 - A-POWER		/
页数	文件大小	规格书
29页	2634K
描述
IC POWER SUPPLY SUPPORT CKT, Power Management Circuit

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APE3520VN4 技术参数

生命周期：	Obsolete	包装说明：	HQCCN,
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.72
可调阈值：	YES	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	S-XQCC-N24	信道数量：	5
功能数量：	1	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG
最大供电电压 (Vsup)：	28 V	最小供电电压 (Vsup)：	6.5 V
标称供电电压 (Vsup)：	12 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子位置：	QUAD	Base Number Matches：	1

Advanced Power

Electronics Corp.

APE3520/A

APPLICATION INFORMATION (Continued)

Layout Considerations

The switching power stages require more attention in PCB layout. Keep the high current paths short.

Separate the ground terminals. Four-layer board is recommended. Use two middle layers as ground planes,

with interconnections between top and bottom layers as needed. Below lists help start layout work.

1. Minimize the resistance by keeping the power component group together with short and wide trace (60mil

at least).

2. Connect the drivers of UDx and LDx close to the gate of high-side and low-side MOSFET with short trace

as possible to reduce stray inductance.

3. Keep sensitive analog node (FBx, ENTRIPx, VOUTx, REF, TON and SKIP) away from high-speed

switching loop to avoid noise coupling.

4. Place feedback resistors near FBx and GND pin with short wire and should be far away to the noise

source, such as switching loop. Use ground plane to shield feedback trace from power components.

5. The current limit setting resistor, R_ENTRIPx, should connect to ENTRIPx and GND pin directly.

6. Place the bypass capacitor of VIN, REF, VREG5, and VREG3 close to the pin.

7. Group the analog ground connection of the VREF bypass capacitors, VFBx, and ENTRIPx. Connect the

analog ground plane directly to GND pin of the IC.

8. Group the power ground connection of the VIN capacitor, VOUT capacitor, the low-side MOSFETs,

charge pump circuit, VREG5 and VREG3 as close as possible. Connect this power ground plane directly

to PGND pin of the IC.

9. PGND is used as the positive current sensing node so PGND should be connected to the source terminal

of the bottom MOSFET.

10. Use plane connection between GND (analog ground) and PGND (power ground) near the IC.

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