Datasheet > AP1705AW5

AP1705AW5

更新时间： 2022-12-01 20:01:45

品牌	Logo	应用领域
易亨 - ANACHIP		/
页数	文件大小	规格书
13页	288K
描述
Power Management Circuit,

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数据手册

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AP1705AW5 数据手册

AP1705/6/7

Processor Supervisory Circuits

Timing requirements (at R_L=1mΩ, C_L=50pF, T_A=25^oC)

Sym.

Parameter

at V_CCV_CC=V_IT-+0.2V, V_CC=V_IT--0.2V

V_CC>V_IT-+0.2V, V_IL=0.3×V_CC, V_IH=0.7×V_CC

at WDI V_CC>V_IT-+0.2V, V_IL=0.3×V_CC, V_IH=0.7×V_CC

Test Conditions

Min.

0.5

Typ.

Max. Unit

µs

Pulse

Width

t_W

at MR

Switching Characteristics (at R_L=1mΩ, C_L=50pF, T_A=25^oC)

Sym.

Parameter

Test Conditions

Min.

Typ.

Max. Unit

V_CC>V_IT-+0.2V,

t_toutWatchdog Time Out AP1705/6/7

0.9

1.6

2.5

See timing diagram

V_CC>V_IT-+0.2V,

t_dDelay Time

AP1705/6/7

120

200

300

See timing diagram

V_CC>V_IT-+0.2V,

Propagation (Delay)

MR to RESET

delay (AP1705/7)

V_IL=0.3×V_CC

0.1

µs

Time,

t_PHL

V_IH=0.7×V_CC

V_IL=V_IT--0.2V,

V_IH=V_IT-+0.2V

V_CC>V_IT-+0.2V,

High-to-low-level

Output

V_CCto RESET delay

Propagation (Delay)

Time,

MR to RESET delay

(AP1706/7)

V_IL=0.3×V_CC

0.1

t_PLH

V_IH=0.7×V_CC

V_IL=V_IT--0.2V,

V_IH= V_IT-+0.2V

Low-to-high-level

Output

V_CCto RESET delay

(AP1706/7)

Application Circuit

V_CC

100nF

V_CC

RESET

V_CC

RESET

AP1705/6/7

MR WDI

I/O

GND

Anachip Corp.

www.anachip.com.tw

Rev. 1.0 Nov. 17, 2005

5/13

1 2 3 456 7 8...13

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