AP1250CMP

更新时间： 2024-11-29 06:37:15

品牌	Logo	应用领域
富鼎先进 - A-POWER		稳压器
页数	文件大小	规格书
5页	414K
描述
2A Sink/Source Bus Termination Regulator

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AP1250CMP 数据手册

Advanced Power

Electronics Corp.

AP1250CMP

2A Sink/Source Bus Termination Regulator

Description

Features

The AP1250CMP is a simple, cost-effective and ꢀ Ideal for DDR-I, DDR-II and DDR-III V_TTApplications

high-speed linear regulator designed to generate ꢀ Sink and Source 2A Continuous Current

termination voltage in double data rate (DDR) ꢀ Integrated Power MOSFETs

memory system to comply with the JEDEC SSTL_2 ꢀ Generates Termination Voltage for SSTL_2, SSTL

and SSTL_18 or other specific interfaces such as

_18, HSTL, SCSI-2 and SCSI-3 Interfaces.

HSTL, SCSI-2 and SCSI-3 etc. devices ꢀ High Accuracy Output Voltage at Full-Load

requirements. The regulator is capable of actively ꢀ Output Adjustment by Two External Resistors

sinking or sourcing up to 2A while regulating an ꢀ Low External Component Count

output voltage to within 40mV. The output ꢀ Shutdown for Suspend to RAM (STR) Functionality

termination voltage cab be tightly regulated to track

with High-Impedance Output

1/2V^DDQby two external voltage divider resistors or ꢀ Current Limiting Protection

the desired output voltage can be pro-grammed by ꢀ On-Chip Thermal Protection

externally forcing the REFEN pin voltage.

ꢀ

Available in ESOP-8 (Exposed Pad) Packages

The AP1250CMP also incorporates a high-speed ꢀ V_INand V_CNTLNo Power Sequence Issue

differential amplifier to provide ultra-fast response in ꢀ RoHS Compliant and 100% Lead (Pb)-Free

line/load transient. Other features include extremely

Application

low initial offset voltage, excellent load regulation,

ꢀ

Desktop PCs, Notebooks, and Workstations

Graphics Card Memory Termination

Set Top Boxes, Digital TVs, Printers

Embedded Systems

current limiting in bi-directions and on-chip thermal

shut-down protection.

The AP1250CMP are available in the ESOP-8

(Exposed Pad) surface mount packages.

Active Termination Buses

Pin Configuration

DDR-I, DDR-II and DDR-III Memory Systems

Block Diagram

ESOP-8 (MP)

(Top View)

VIN

GND

REFEN

VOUT

GND

VCNTL

Pin Description

Pin Name

Pin function

V_IN

Power Input

Ground

GND

V_CNTL

REFEN

V_OUT

Gate Drive Voltage

Reference Voltage input and Chip Enable

Output Voltage

200901074

12 3 4 5

中文翻译

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