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AN701

更新时间: 2022-11-25 11:11:34
品牌 Logo 应用领域
威世 - VISHAY 转换器开关控制器
页数 文件大小 规格书
20页 1116K
描述
Designing High-Frequency DC-to-DC Converters With the Si9114A Switchmode Controller

AN701 数据手册

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AN701  
Vishay Siliconix  
Typical open loop voltage gain is 77 dB, and unity gain  
bandwidth is typically 2.7 MHz. The soft-start circuit (see Pin 7  
description) forces the output to within 0.7 V above ground,  
and additional clamp diodes limit the positive output excursion  
to within 2xVBE above VREF . Operation at high frequency  
allows high closed loop bandwidths and permits excellent  
transient response to both input and output changes. Under  
normal operation, a small 100 pF bypass capacitor is  
recommended from NINV to Comp to increase high-frequency  
noise rejection. This should be calculated, however, in  
conjunction with the loop dynamics.  
oscillations may occur. These can be prevented with the use  
of long soft-start times. The soft-start pin can also be used as  
a non-latching shutdown pin by connecting it to VIN. This  
approach allows a shutdown with soft re-start.  
PINS 8 AND 9 - OSCILLATOR  
The oscillator circuit uses external timing components RT and  
CT. An internal divide-by-two prevents pulses with greater than  
50% duty cycle, so that core saturation can be avoided. When  
the RT terminal is connected to VCC, comparator C2  
disconnects the oscillator output from the SYNC terminal using  
SW1, and allows an external oscillator circuit to take control of  
the current mode comparator circuit.  
PIN 7: SOFTĆSTART  
The soft-start circuit is designed to help dc-to-dc converters  
start in an orderly manner and reduce component stress. The  
output of the error amplifier is clamped by a PNP transistor.  
The current programmed by RT defines the charging current of  
CT and the on and off times with the following design  
equations:  
The external capacitor CSS is supplied by a 20-mA current  
source and will charge linearly to 4.6 V. In the event of an  
under-voltage lockout (or during start-up), this capacitor is held  
low.  
1.025 x RT x CT  
8
(1)  
(2)  
(3)  
tON  
+
where R = 25 W  
tOFF + 5 x Rql x CT  
ql  
1
tON ) tOFF  
1
2
Feedback  
Error Amp  
fOSC  
+
x
ǒ
Ǔ
Actual values taken from a prototype board have been  
plotted (Figure 6), and are a close match (except for 47 pF,  
where stray parasitics have more significant effect).  
V
REF  
Comparator  
4.6 V  
20 mA  
1000  
47 pF  
100 pF  
150 pF  
200 pF  
C
SS  
100  
UV-low  
Note: These curves were measured in  
a
board with 3.5 pF of  
Figure 5 Soft-Start  
external parasitic capacitance.  
10  
Soft-start is a very important feature and has many beneficial  
effects, especially in applications connecting to telecom lines  
where source impedances are high. In such cases, there is an  
initial start-up current caused by the input capacitor, followed  
by a secondary peak caused by the converter running at  
maximum duty cycle while trying to reach regulation. Where  
large output capacitances and peak loads are encountered,  
10  
100  
(kW)  
1000  
R
OSC  
Figure 6 Oscillator Frequency Selection  
Document Number: 70575  
16-Jan-01  
www.vishay.com  
4

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