Datasheet > AN3727

AN3727

更新时间： 2024-02-01 06:12:34

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
6页	78K
描述
MA31750 - Interrupt operations

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AN3727 数据手册

AN3727: MA31750 - Application Note 4

AN3727

MA31750 - Interrupt Operations

Application Note

Replaces July 2000 version, AN3727-4.0

AN3727-4.1 July 2002

This applications note details the interrupt handling

operations of the NMA31750.

HARDWARE CONSIDERATIONS

The user interrupts, PWRDN and INT02N-INT15N, can be

defined as being edge or level sensitive by the State of bit 4 in

the configuration word. If edge sensitivity is selected, an

interrupt pulse exceeding the minimum width (specified in the

data sheet), appearing at any time in the cycle, will latch an

interrupt request. Another interrupt request cannot be detected

on that interrupt line until the previous one has cleared.

If level sensitivity is selected, an interrupt will be requested

whenever the interrupt signal is active as the Pl latches ( ie. the

same interrupt could be latched multiple times). It is the user’s

responsibility to deactivate any unwanted external interrupts.

INTAKN is asserted low whilst the processor reads the

interrupt service pointer (part of the microcoded interrupt

service routine). This event may be used to identify and

release the interrupt currently being serviced. Figure 1 is a

representation of the CPU interrupt latching circuitry.

INTRODUCTION

The MA31750 has 16 interrupts: 9 of these interrupts are

available to the system as external interrupts to the processor,

The remaining 7 are internally generated by the MA31750.

Interrupts can occur at any time and are latched into the

Pending Interrupt register (Pl). However, they are not serviced

until completion of the currently executing MIL-STD1750

instruction.

MIL-STD-1750 makes provision for interrupt software

control via l/O commands. These l/O commands are internally

implemented by the MA31750. They provide an enable/

disable facility (without preventing the latching of interrupt

requests into the Pl) and a means of manipulating the interrupt

Mask Register (MK), the Pl and the Fault Register (FT)

contents.

Global_Clear

Clear_Bit

Pending_

Interrupt

Sync

ehb

eha

Interrupt

Sync_Signal

Edge_or_Level

Internal_Interrupt

Clock

Figure 1: Edge and Level Interrupt Latching Circuit

1/6

12 3 4 5 6

中文翻译

下载PDF

与AN3727相关器件

型号	品牌	获取价格	描述	数据表
AN3728	FREESCALE	获取价格	Media Compatibility for IPS PRT Pressure Sensors
AN3729	ETC	获取价格	MA31750 - Bus arbiter
AN3791	ETC	获取价格	VTR X-VALUE SHIFT CIRCUIT
AN3792	PANASONIC	获取价格	Analog Circuit, 1 Func, BIPolar, PDIP18, 0.300 INCH, PLASTIC, DIP-18
AN3793	PANASONIC	获取价格	Interface Circuit, PDIP18, PLASTIC, SIL-18
AN3794N	PANASONIC	获取价格	Analog Circuit, 1 Func, BIPolar, PDIP18, 0.300 INCH, PLASTIC, DIP-18
AN3795	PANASONIC	获取价格	Analog Circuit, 1 Func, PDIP18, PLASTIC, SIL-18
AN3795N	PANASONIC	获取价格	Analog Circuit, 1 Func, BIPolar, PDIP18, 0.300 INCH, PLASTIC, DIP-18
AN38	PANASONIC	获取价格	Cylinder Hall motor driving IC for VCR
AN38	FAIRCHILD	获取价格	0.300-INCH SEVEN SEGMENT DISPLAYS