coulombs. If the DAC were forced to a ‘‘11 0000 0000’’ or
300 code, the voltage, which is output from the 2 MSB
input capacitor (/16 smaller in value to properly reduce the
significance of the last 4 bits.
HEX
section, would be V
charge via the 48C capacitor, so this charge, Q300
/2. This is converted to an input
REF
FULL-SCALE TRIM
, be-
HEX
Full-scale (or ‘‘gain’’) errors are trimmed by introducing an
additional correcting charge into the summing node of the
comparator. This is done in steps; for example, no full-scale
correction is used on the first (/4 of the analog input voltage
range (near zero). The next range receives (/3 of the total
FS correcting charge, then )/3, and finally the full charge is
introduced in the last section. This sequencing of the FS
trim is achieved by dynamically altering the input capaci-
tance from no capacitance to C/2, to C/4, and finally to
3C/4. This is the reason for the extra input capacitor and
the added switches, which are shown in the FS trim section
of Figure 6.
comes:
V
REF
e
c
48C
Q300
HEX
2
e
2.5V
and as
then
V
/2
REF
e
Q300
HEX
2.5 (48)C
or
e
Q300
120C
HEX
which ratios to the analog full-scale charge, Q
as
AFS
Q300
HEX
120C
160C
e
e
*/4 FS
APPLICATIONS
Q
AFS
The standard applications of the 8-bit ADC0804 series* can
now easily be extended to 10 bits by simply plugging in the
new ADC1001 10-bit part. In addition, a 24 pin product
(ADC1021) is also available, which brings all 10 bits out for
a 16-bit data bus application.
which is the proper weight for the 300
code.
HEX
HEX
Similarly, the ‘‘00 1000 0000’’ or 080
code should re-
quire (/8 (V ) at the analog input (neglecting the effects of
REF
the (/2 LSB offset voltage shift) to balance. This is the output
of the 8 LSB section with a binary code of ‘‘1000 0000’’
input to this DAC section. The charge from the analog input,
The zero offsetting (by introducing a DC shifting voltage into
pin) can be used to accommodate analog input
)
the V
Q , which corresponds to an analog input voltage of (/8
A
b
IN(
voltages which do not swing to ground. The V
/2 input
REF
V , is given by:
REF
voltage can also be reduced to accommodate a reduced
span of analog input voltages. Finally, system designers can
use the same PC board for either an 8-bit or a 10-bit product
to take advantage of the standard pinouts used for these
A/D converters.
e
Q
A
(/8(V
) (32C)
REF
The output voltage of the 8-bit DAC section for 080
code is (/2 (V
HEX
)/2, so the charge input by this DAC, Q ,
REF DAC
is given by
(V
)
REF
e
Q
(/2
(16C),
DAC
CONCLUSIONS
2
The multiple, input, sampled-data voltage comparator al-
lows many benefits in both the design and application flexi-
bility of monolithic A/D converters. This revolutionary con-
cept has reduced the die size of A/Ds, allows many product
benefits, and appears to be the optimum solution for the
realization of a low cost, high performance, monolithic A/D
converter line.
and this ratios to the analog input change, Q , as
A1
Q
(/2 (V
/2) (16C)
) (32C)
DAC
REF
e
e
1
Q
(/8 (V
REF
A
as expected. The 4 LSB grouping of this 8-bit DAC uses an
*For further details see data sheet.
5
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