This 2 resistor ladder will produce linearity errors in only 2 of
the segments of the overall A/D transfer characteristic, be-
data is left-justified and transferred, most significant byte
first. This allows a single read cycle to pick up a valid 8-bit
representation (the 8 MSBs) and can save time if this is all
the resolution that is required on a particular analog chan-
nel. A second read cycle will pick up the 2 LSBs of the 10-bit
data word. The 6 LSB positions are set to zero in this sec-
ond byte. An internal byte counter keeps track of the byte
sequencing so multiple, double-read cycles can be made, if
desired.
e
cause there will be no errors in the first segment (2 MSBs
0), because V for this code is 0V. Similarly, if we assume
DAC
that the input capacitors ratio properly, there will be no lin-
earity errors in the last segment, because the full V is
REF
as compared
to the analog input voltage, via C ). Any mismatch between
sampled (then is weighed to produce */4 V
REF
IN
the C of the analog differential input voltage and the C
of the DACs will cause a full-scale error, not a linearity error.
IN
IN
The problem of properly biasing a 5 V
when operating from only a single 5 V
reference circuit
power supply volt-
DC
The two end segments are therefore both free of linearity
errors and an additional benefit is that any error in the exact
value of the tap voltage on a 2 resistor divider has the natu-
ral characteristic that the error is the same magnitude on
DC
age was handled on the 8-bit part by reducing the operating
reference voltage for the internal DAC to only 2.5 V . This
DC
can be designed to still provide a 5V full-scale for the A/D
by simply doubling the sizes of all of the DAC input capaci-
tors to the comparator. This technique was also used for
this 10-bit product. The reference voltage can also be fur-
ther reduced in magnitude to increase the analog resolution
over a reduced analog input voltage span, if desired.
the (/3 V
REF
and )/3 V voltages, and is simply of opposite
REF
sign. Thus, a linearity trim must provide a single magnitude
of correcting charge, then this same charge is introduced
into the comparator summing mode in one polarity for the
‘‘01’’ 2 MSB code, and then the opposite polarity for the
‘‘10’’ code (a correcting charge is not used for the ‘‘00’’ or
‘‘11’’ codes).
A basic diagram of the DAC and the comparator input sec-
tion of the 10-bit A/D are shown in Figure 6. A simplified
schematic representation has been used for the 8 LSB sec-
tion. This has been shown in more detail in Figure 3 without
THE ADC1001, A 10-BIT A/D
In keeping with the similarity to the previous 8-bit A/D, a 10-
bit product was designed to fit in the same 20 pin (0.3
the V
reduction to V
/2.
REF
REF
×
To understand the scaling shown for the input capacitors,
keep in mind that it is the input charge which is balanced.
This means that a maximum differential analog input voltage
of 5V would produce an input charge of 5 x 32C or 160C
wide) package and to use the same pinouts. Now a custom-
er can easily interchange from an 8 to a 10-bit A/D. This
allows for a range of performance variation in his end prod-
ucts while using the same PC board.
The problem of getting the 10-bit output of the A/D onto an
8-bit data bus is handled by reading two 8-bit bytes. The
TL/H/8716–6
FIGURE 6. The DAC and Comparator Input Section
4
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