A more useful voltage comparator results from a sampled-
data approach, which involves switches and capacitors.
Now, input voltages are converted to input charges by the
use of input capacitors, and the resulting charges are then
algebraically added at a ‘‘charge summing’’ node.
The differential input feature of this comparator has allowed
an unusual resistor ladder to be used for the DAC. Notice
that the top three resistors (each labeled ‘‘R’’) have (/4 V
REF
across them and the lower resistors (each labeled ‘‘R/4’’)
have (/16 V across them. The comparator, therefore, al-
REF
lows the increased resolution of the S2 selected voltages to
be ‘‘fitted into’’ each section of the upper or S1 selected
voltages. In this way, the first 4 bits of this differential DAC,
or ‘‘DDAC,’’ are realized.
A multiple, differential input, sampled-data comparator is
shown in Figure 2 with the switches in the zeroing cycle.
The input-output short, which is accomplished with SW5
around the inverting gain block (provided by a logic invert-
er), causes this stage to bias at a fixed DC voltage. For
example, a standard CMOS inverter will bias at approxi-
mately one half of the power supply voltage. Notice that at
this time the input switches, SW2 and SW4, are precharging
b
the input capacitors with the ( ) input voltages of the differ-
ential inputs. These input capacitors will serve as storage
b
elements to remember both of the ( ) input voltages and
the biasing voltage of the gain stage.
This same 4-bit trick is used again via the left side decoding
switches, S3 and S4. These same voltage values provide
charge which is reduced in significance by 16:1, making the
input capacitor for this section a factor of 16 smaller. This
now provides the least significant 4-bit group. The additional
capacitor, C, and the lowermost two resistors (labeled
‘‘R/8’’) supply a (/2 LSB overall DAC offset voltage. This is
g
used in A/Ds to center the natural (/2 LSB quantization
uncertainty of the A/D about the integer LSB values of ana-
These zeroing switches are then opened. The gain stage is
now active and will respond to any deviations in the input
voltage. An input voltage results when the switches SW1
and SW3 are subsequently both closed. As shown in the
figure, DV1 is positive, which inputs a charge, Q1, propor-
log input voltage. (This is (/2 LSB voltage is added to the
analog input to cause the 00 to 01 code change of
HEX HEX
the A/D to occur at any analog input voltage value of only
(/2 LSB.)
e
tional to the value of C1, (Q1
DV1C1). If DV2 is negative,
If we are to use this basic 8-bit design for a 10-bit converter,
we must make these 8 bits the least significant of the 10-bit
data word. This can easily be done by again scaling the
capacitor sizes. Further, 2 additional MSBs must be added:
here is where another trick comes in.
a charge, Q2, will be removed from the charge summing
node. If the charges Q1 and Q2 are balanced, there is no
net change in the input voltage of the inverting gain block.
These switches are dynamically cycled by a clock and the
system is zeroed prior to each measuring interval. This is
the same operating mode as has been used years ago by
the auto-zeroed or chopper-stabilized op amps. A sufficient
number of these stages are capacitor-coupled to provide an
adequate overall gain for the comparator.
A NOVEL WAY OF ADDING 2 MSBs
2
The 2 MSBs of the DAC will control 2 , or 4, voltages. If
these are chosen as V
, ground, (/3 V
REF
and )/3 V
REF REF
we have an unusually beneficial situation. Notice that the
differential voltage input feature of the sampled-data com-
parator allows picking up the two intermediate voltages ((/3
MAKING AN 8-BIT A/D
and )/3 V
) from a resistor divider with only one tap, as
REF
This sampled-data comparator was made the heart of an 8-
bit A/D converter, as shown in Figure 3. The comparator
now has four differential voltage inputs; one for the analog
inputs and three for the DAC. The first 4 MSBs of the 8-bit
A/D are supplied by the DAC switches, S1 and S2. As
shown, the positions of S1 and S2 correspond to the digital
code, ‘‘10 00,’’ for the first 4 bits of the 8-bit word. This
shown in Figure 4. These odd voltage values ((/3 and )/3
) from this 2 MSB DAC are ‘‘cleaned up’’ simply by
scaling the size of the input capacitor which is used for this
V
REF
DAC section by a factor of */4. This will, therefore, provide
, )/4 V
REF REF
the (/4 V
REF
increments 0, (/4 V
and */4 V ,
REF
which are necessary for the 2 MSBs. Now the basic 8-bit
circuit can be used a total of 4 times, with each referenced
should input V
ing */4 V
/2 from the DAC. Note that S1 is select-
and S2 is selecting (/4 V , and these voltages
REF
to one of these (/4 V
REF
input voltage range of 0 to V
as shown in Figure 5.
values. This will cover the analog
with 10 bits of resolution,
REF
REF
REF
are the first differential pair which is sampled by SW1 and
SW2 at the start of a successive approximation search. This
b
provides (*/4 V
the DAC.
(/4 V ) or (/2 V
REF
as required from
REF
REF
* Switches are shown in the ‘‘zeroing’’ cycle
TL/H/8716–2
FIGURE 2. A Multiple, Differential Input Sampled-Data Comparator or Charge Summing Circuit
2
5秒后页面跳转
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
一文带你了解压敏电阻器在直流电路中的过压保护作用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
