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AN-768

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飞兆/仙童 - FAIRCHILD		/
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ECL Backplane Design

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Fairchild Semiconductor

Application Note

March 1991

AN-768

Revised May 2000

ECL Backplane Design

INTRODUCTION

ECL/TTL PERFORMANCE PARAMETERS

Designers are constantly trying to improve the performance

of their systems. In many applications, this can be accom-

plished by increasing the speed of the system backplane.

As system bandwidth requirements exceed 50 MHz, ECL

is the logic of choice over TTL. ECL devices are designed

for transmission line applications which means that ringing,

reflections, and noise are minimized. These problems are

not easily handled with TTL devices. ECL devices are the

fastest in common use today and have increased steadily

in popularity over the past 10 years with the additional

speed requirements of many systems. With this popularity

have come improvements such as increased reliability,

power reduction, and better ESD protection.

There are several advantages associated with using ECL.

ECL is a non-saturating logic, as opposed to TTL, which

results in much faster switching speeds for drivers tied to

the backplane. The ECL circuit contains a differential

amplifier with its outputs being a function of the difference

between two input voltages; where one is a reference volt-

age (V_BB) and the other (V_IN) is a logic HIGH or LOW (see

Figure 1). The differential inputs determine which path the

constant current (I_S) will flow. An internal reference circuit

establishes a stable V_BBvoltage of −1.32V. When a LOW

level (−1.730V typical) signal is applied to V_IN, Q1 “cuts

off”. Transistor Q2 is turned on with collector current

through the Q2 branch being supplied by the current

source (I_S). This sets up a LOW level on A and a HIGH

ECL devices today offer the flexibility of single-ended or dif-

ferential backplanes. Fairchild Semiconductor has

responded to the increasing need for ECL backplanes by

introducing octal registers, latches and translators. The

registers and latches offer the flexibility to drive a 25Ω (with

cutoff) or 50Ω load impedance. The 25Ω drivers are

intended to drive a 50Ω transmission line which is doubly

terminated in its characteristic impedance, or a single low

impedance 25Ω line. Considerations such as transmission

line media (microstrip, stripline, coaxial, twisted pair, etc.)

terminations, connectors, power planes and loading effects

must all be understood to design the optimum system.

level on the compliment output as long as the output is

properly terminated.

A HIGH level (−0.970V typical) applied to V_INwill then turn

on Q1 and “cutoff” Q2. This will set up a HIGH voltage level

on A and a LOW level on its compliment. Since the current

is nearly constant at all times, even during switching, cur-

rent spikes are minimized on the power supply. This is an

important feature of ECL (unlike TTL) because the power

requirement is unaffected by frequency. ECL becomes

more favorable at frequencies above 50 MHz with a 50%

duty cycle. The outputs of ECL devices typically require an

external termination resistor and termination voltage (V_TT

)

to develop the proper output voltage levels.

FIGURE 1. ECL Gate

AN010910

www.fairchildsemi.com

12 3 4 5 6 7 8

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