Datasheet > AMIS710401-A4

AMIS710401-A4

更新时间： 2024-01-25 18:19:08

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描述
Image Sensor,

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AMIS710401-A4 技术参数

生命周期：	Transferred	Reach Compliance Code：	unknown
风险等级：	5.76	Base Number Matches：	1

AMIS710401-A4 数据手册

AMIS710401-A4: 400dpi CIS Module

Data Sheet

Red 600nm LED Light Source

Table 8: Recommended Operating Conditions at 25°C

LED Light Source

660nm Red LED

Note:

Parameter

VLED

Min.

Typ.

5.0

Max.

5.5

Units

(1) The maximum clock speed is limited by the LED power of the modules’ light source.

The minimum clock speed is determined by the longest tolerable integration time. Because of the leakage current build up, the integration time is recommended to

be no greater than 10ms.

9.0 Reset Level and Video Sampling Time

Figure 3: Reset Level and Sample Time

Figure 3 shows the video signal waveform and details a single pixel. The signal output waveform is shown referenced to the input clock

waveform. Also shown is the terminology used to define the dark and bright output levels, Vp, and the recommended pixel sampling

times, tsst. Also shown is the clock to video reset time delay, tdl.

The dark level is defined by using the module imaging on a black target or with the light source turned off. The dark level is then

measured from ground or 0V. The reset level is a reference level of the reset switch, which is not necessarily at ground. The reason for

this is that after the reset operation, the video signal is passed through an amplifier, which may have some offsets. The difference

between the dark level and reset level is called the pedestal, PED. Hence, the reset level will sit below the dark level.

The video pixels demonstrated in this graph are ideal waveforms from a CIS module, using a phototransistor imaging structure. The

video output at high speeds, such as 5.0MHz, does not instantly rise to its final value, although if it is given enough time it would

eventually approach its steady state value (in order of milliseconds). However, at high speeds it is impractical to wait until a final stable

value is reached. The suggested sampling point, tsst, is therefore a few nanoseconds prior to the signal falling edge of Vp.

AMI Semiconductor – Jun. 06, M-20589-001

www.amis.com

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