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AMDM-125J PDF预览

AMDM-125J

更新时间: 2024-11-06 06:37:07
品牌 Logo 应用领域
RHOMBUS-IND 延迟线逻辑集成电路光电二极管
页数 文件大小 规格书
1页 39K
描述
AMDM Series FAST / TTL Buffered 5-Tap Delay Modules

AMDM-125J 技术参数

是否Rohs认证: 不符合生命周期:Active
零件包装代码:SOIC包装说明:SOJ, SMDIP8,.3
针数:8Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:N其他特性:MAX RISE TIME CAPTURED
系列:TTLJESD-30 代码:R-PDSO-J8
负载电容(CL):10 pF逻辑集成电路类型:ACTIVE DELAY LINE
功能数量:1抽头/阶步数:5
端子数量:8最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SMDIP8,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5 V
最大电源电流(ICC):65 mA可编程延迟线:NO
Prop。Delay @ Nom-Sup:125 ns认证状态:Not Qualified
座面最大高度:6.73 mm子类别:Delay Lines
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:J BEND端子节距:2.54 mm
端子位置:DUAL总延迟标称(td):125 ns
Base Number Matches:1

AMDM-125J 数据手册

  
AMDM Series FAST / TTL Buffered 5-Tap Delay Modules  
Electrical Specifications at 25OC  
Low Profile 8-Pin Package  
Two Surface Mount Versions  
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)  
FAST/TTL  
Tap-to-Tap  
(ns)  
FAST/TTL Logic Buffered  
5 Equal Delay Taps  
5-tap 8-Pin DIP  
Tap 1  
Tap 2  
Tap 3  
Tap 4  
Total - Tap 5  
AMDM-7  
AMDM-9  
3.0  
3.0  
4.0  
4.5  
5.0  
6.0  
6.0  
7.5  
7 ± 1.0  
9 ± 1.0  
1 ± 0.5  
1.5 ± 0.5  
2 ± 0.7  
Operating Temperature  
Range 0OC to +70OC  
AMDM-11  
AMDM-13  
AMDM-15  
AMDM-20  
AMDM-25  
AMDM-30  
AMDM-35  
AMDM-40  
AMDM-50  
AMDM-60  
AMDM-75  
AMDM-100  
AMDM-125  
AMDM-150  
AMDM-200  
AMDM-250  
AMDM-350  
AMDM-500  
3.0  
5.0  
7.0  
9.0  
11 ± 1.0  
13 ± 1.5  
15 ± 1.5  
20 ± 2.0  
25 ± 2.0  
30 ± 2.0  
35 ± 2.0  
40 ± 2.0  
50 ± 2.5  
60 ± 3.0  
75 ± 3.75  
100 ± 5.0  
125 ± 6.25  
150 ± 7.5  
200 ± 10.0  
250 ± 12.5  
350 ± 17.5  
500 ± 25.0  
3.0  
5.5  
8.0  
10.5  
12.0  
16.0  
20.0  
24.0  
28.0  
32.0  
40.0  
48.0  
60.0  
80.0  
100.0  
120.0  
160.0  
200.0  
280.0  
400.0  
2.5 ± 1.0  
3 ± 1.0  
14-Pin Versions: FAIDM Series  
SIP Versions: FSIDM Series  
3.0  
6.0  
9.0  
4.0  
8.0  
12.0  
15.0  
18.0  
21.0  
24.0  
30.0  
36.0  
45.0  
60.0  
75.0  
90.0  
120.0  
150.0  
210.0  
300.0  
4 ± 1.5  
Low Voltage CMOS Versions  
refer to LVMDM / LVIDM Series  
5.0  
10.0  
12.0  
14.0  
16.0  
20.0  
24.0  
30.0  
40.0  
50.0  
60.0  
80.0  
100.0  
140.0  
200.0  
5 ± 2.0  
6.0  
6 ± 2.0  
7.0  
7 ± 2.0  
AMDM 8-Pin Schematic  
8.0  
8 ± 2.0  
Vcc  
Tap1 Tap3 Tap5  
10.0  
12.0  
15.0  
20.0  
25.0  
30.0  
40.0  
50.0  
70.0  
100.0  
10 ± 2.0  
12 ± 2.0  
15 ± 2.5  
20 ± 3.0  
25 ± 3.0  
30 ± 3.0  
40 ± 4.0  
50 ± 5.0  
70 ± 5.0  
100 ± 10.0  
8
7
6
5
1
2
3
4
GND  
IN  
Tap2 Tap4  
** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1.  
TEST CONDITIONS -- FAST / TTL  
VCC Supply Voltage................................................ 5.00VDC  
Input Pulse Voltage ................................................... 3.20V  
Input Pulse Rise Time ....................................... 3.0 ns max.  
Input Pulse Width / Period ........................... 1000 / 2000 ns  
1. Measurements made at 25OC  
2. Delay Times measured at 1.50V level of leading edge.  
3. Rise Times measured from 0.75V to 2.40V.  
4. 10pf probe and fixture load on output under test.  
DImensions in Inches (mm)  
.285  
.505  
(12.83)  
MAX.  
(7.24)  
MAX.  
.020  
(0.51)  
TYP.  
.250  
DIP  
DIP  
(6.35)  
MAX.  
.010  
(0.25)  
TYP.  
.120  
(3.05)  
MIN.  
.300  
(7.62)  
OPERATING SPECIFICATIONS  
VCC Supply Voltage ................................... 5.00 ± 0.25 VDC  
ICC Supply Current .................................... 48 mA Maximum  
Logic “1” Input: VIH ....................... 2.00 V min., 5.50 V max.  
.365  
(9.27)  
MAX.  
.020 .050  
.100  
(0.51)  
TYP.  
(2.54)  
(1.27)  
TYP. TYP.  
I
IH ............................... 20 µA max. @ 2.70V  
.285  
(7.24)  
MAX.  
.505  
(12.83)  
MAX.  
Logic “0” Input: VIL .......................................... 0.80 V max.  
IIL ............................................ -0.6 mA mA  
VOH Logic “1” Voltage Out .................................. 2.40 V min.  
VOL Logic “0” Voltage Out ............................... 0.50 V max.  
PWI Input Pulse Width ............................. 40% of Delay min.  
Operating Temperature Range ............................ 0O to 70OC  
Storage Temperature Range ...................... -65O to +150OC  
.250  
(6.35)  
MAX.  
G-SMD  
G-SMD  
.008 R  
(0.20)  
.010  
(0.25)  
TYP.  
.030  
(0.76)  
TYP.  
.430 (10.92)  
.400 (10.16)  
.015  
(0.38)  
TYP.  
.020 .050  
.100  
(2.54)  
TYP.  
(0.51)  
(1.27)  
TYP. TYP.  
P/ N De sc rip tion  
AMDM - XXX X  
Buffered 5 Tap Delay  
Molded Package Series:  
.285  
(7.24)  
MAX.  
.505  
(12.83)  
MAX.  
8-pin DIP: AMDM  
Total Delay in nanoseconds (ns)  
.265  
(6.73)  
MAX.  
Lead Style: Blank = Thru-hole  
G = “Gull Wing” SMD  
J = “J” Bend SMD  
J-SMD  
J-SMD  
.285 (7.24)  
.260 (6.60)  
.020 R  
(0.51)  
Examples: AMDM-25G = 25ns (5ns per tap)  
74F/TTL, 8-Pin G-SMD  
.030  
(0.76)  
TYP.  
.020 .050  
.100  
(2.54)  
TYP.  
.330 (8.38)  
MAX.  
AMDM-100 = 100ns (20ns per tap)  
74F/TTL, 8-Pin DIP  
(0.51)  
TYP.  
(1.27)  
TYP.  
For other values & Custom Designs, contact factory.  
Specifications subject to change without notice.  
AMDM 9901  
15801 Chemical Lane, Huntington Beach, CA 92649-1595  
Phone: (714) 898-0960 FAX: (714) 896-0971  
www.rhombus-ind.com email: sales@rhombus-ind.com  
Rhombus  
Industries Inc.  

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