Datasheet > AM486DE2

AM486DE2

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
超微 - AMD		微处理器
页数	文件大小	规格书
52页	1154K
描述
8-Kbyte Write-Through Embedded Microprocessor

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AM486DE2 数据手册

FINAL

Am486 DE2

8-Kbyte Write-Through Embedded Microprocessor

DISTINCTIVE CHARACTERISTICS

■ High-Performance Design

■ Complete 32-Bit Architecture

— 66-MHz operating frequency

— Address and data buses

— All registers

— Frequent instructions execute in one clock

— 105.6-million bytes/second burst bus at 33 MHz

— Flexible write-through address control

— Dynamic bus sizing for 8-, 16-, and 32-bit buses

— Soft reset capability

— 8-, 16-, and 32-bit data types

■ Standard Features

— 3-V core with 5-V-tolerant I/O

— Binary compatible with all Am486^®DX

and Am486DX2 microprocessors

■ High On-Chip Integration

— Wide range of support available through the

AMD FusionE86^SMProgram

— 8-Kbyte unified code and data cache

— Floating-point unit

■ IEEE 1149.1 JTAG Boundary-Scan Compatibility

— Paged, virtual memory management

■ Enhanced System and Power Management

■ Supports Environmental Protection Agency's

Energy Star program

— Stop clock control for reduced power

consumption

— 3-V operation reduces power consumption up to

40%

— Industry-standard, two-pin System Management

Interrupt (SMI) for power management indepen-

dent of processor operating mode and operating

system

— Energy management capability provides an ex-

cellent base for energy-efficient design

— Works with a variety of energy-efficient, power-

managed devices

— Static design with Auto Halt Power-Down support

■ 208-Lead SQFP or 168-Pin PGA Package

— Wide range of chipsets supporting SMM avail-

able to allow product differentiation

GENERAL DESCRIPTION

The Am486DE2 microprocessor is an addition to the

AMD Am486 microprocessor family. The Am486DE2

enhances system performance by incorporating flexible

clock control and enhanced SMM.

The Am486DE2 CPU clock control feature permits the

CPU to be stopped under controlled conditions, allowing

reduced power consumption during system inactivity.

The SMM function is implemented with an industry-stan-

dard, two-pin interface.

Publication ID

Revision

Amendment

Issue Date

20037

April 1996

12 3 4 5 6 7...52

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