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AM29LV008BB-80FD PDF预览

AM29LV008BB-80FD

更新时间: 2024-02-26 12:57:30
品牌 Logo 应用领域
飞索 - SPANSION 光电二极管内存集成电路
页数 文件大小 规格书
39页 727K
描述
Flash, 1MX8, 80ns, PDSO40, REVERSE, MO-142CD, TSOP-40

AM29LV008BB-80FD 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP1包装说明:TSOP1-R,
针数:40Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.37最长访问时间:80 ns
其他特性:MINIMUM 1000K WRITE CYCLE; 20 YEAR DATA RETENTION启动块:BOTTOM
数据保留时间-最小值:20JESD-30 代码:R-PDSO-G40
JESD-609代码:e3长度:18.4 mm
内存密度:8388608 bit内存集成电路类型:FLASH
内存宽度:8功能数量:1
端子数量:40字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1-R封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260编程电压:3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40类型:NOR TYPE
宽度:10 mmBase Number Matches:1

AM29LV008BB-80FD 数据手册

 浏览型号AM29LV008BB-80FD的Datasheet PDF文件第2页浏览型号AM29LV008BB-80FD的Datasheet PDF文件第3页浏览型号AM29LV008BB-80FD的Datasheet PDF文件第4页浏览型号AM29LV008BB-80FD的Datasheet PDF文件第5页浏览型号AM29LV008BB-80FD的Datasheet PDF文件第6页浏览型号AM29LV008BB-80FD的Datasheet PDF文件第7页 
Am29LV008B  
8 Megabit (1 M x 8-Bit)  
CMOS 3.0 Volt-only Boot Sector Flash Memory  
DISTINCTIVE CHARACTERISTICS  
Single power supply operation  
Top or bottom boot block configurations  
available  
— Full voltage range: 2.7 to 3.6 volt read and write  
operations for battery-powered applications  
Embedded Algorithms  
— Regulated voltage range: 3.0 to 3.6 volt read and  
write operations and for compatibility with high  
performance 3.3 volt microprocessors  
— Embedded Erase algorithm automatically  
preprograms and erases the entire chip or any  
combination of designated sectors  
Manufactured on 0.32 µm process technology  
— Embedded Program algorithm automatically  
writes and verifies data at specified addresses  
— Compatible with 0.5 µm Am29LV008 device  
Minimum 1,000,000 write cycle guarantee per sector  
20-year data retention at 125°C  
— Reliable operation for the life of the system  
Package option  
High performance  
— Full voltage range: access times as fast as 80 ns  
— Regulated voltage range: access times as fast as  
70 ns  
— 40-pin TSOP  
Ultra low power consumption (typical values at 5  
MHz)  
Compatibility with JEDEC standards  
— 200 nA Automatic Sleep mode current  
— 200 nA standby mode current  
— 7 mA read current  
— Pinout and software compatible with single-  
power supply Flash  
— Superior inadvertent write protection  
— 15 mA program/erase current  
Data# Polling and toggle bits  
Flexible sector architecture  
— Provides a software method of detecting program  
or erase operation completion  
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and  
fifteen 64 Kbyte sectors  
Ready/Busy# pin (RY/BY#)  
— Supports full chip erase  
— Provides a hardware method of detecting  
program or erase cycle completion  
— Sector Protection features:  
A hardware method of locking a sector to prevent  
any program or erase operations within that  
sector  
Erase Suspend/Erase Resume  
— Suspends an erase operation to read data from,  
or program data to, a sector that is not being  
erased, then resumes the erase operation  
Sectors can be locked in-system or via  
programming equipment  
Hardware reset pin (RESET#)  
Temporary Sector Unprotect feature allows code  
changes in previously locked sectors  
— Hardware method to reset the device to reading  
array data  
Unlock Bypass Program Command  
— Reduces overall programming time when issuing  
multiple program command sequences  
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data  
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.  
Publication# 21524 Rev: D Amendment/0  
Issue Date: November 19, 1999  

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