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AM29F040-70PC PDF预览

AM29F040-70PC

更新时间： 2024-11-23 05:26:31
品牌 Logo 应用领域
超微 - AMD 闪存内存集成电路光电二极管
页数 文件大小 规格书
33页 418K
描述
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory

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中文翻译

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AM29F040-70PC 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：PLASTIC, DIP-32针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.38
Is Samacsys：N最长访问时间：70 ns
其他特性：BULK ERASE; AUTOMATIC WRITEJESD-30 代码：R-PDIP-T32
长度：42.164 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1端子数量：32
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX8
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL编程电压：5 V
认证状态：Not Qualified座面最大高度：5.715 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL类型：NOR TYPE
宽度：15.24 mmBase Number Matches：1

AM29F040-70PC 数据手册

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FINAL  
Am29F040  
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only,  
Sector Erase Flash Memory  
DISTINCTIVE CHARACTERISTICS  
■ 5.0 V ± 10% for read and write operations  
— Minimizes system level power requirements  
■ Compatible with JEDEC-standards  
■ Embedded Erase Algorithms  
— Automatically preprograms and erases the chip  
or any combination of sectors  
■ Embedded Program Algorithms  
— Pinout and software compatible with single-  
power-supply Flash  
— Automatically programs and verifies data at  
specified address  
— Superior inadvertent write protection  
■ Package options  
■ Data Polling andToggle Bit feature for detection  
of program or erase cycle completion  
— 32-pin PLCC  
■ Erase suspend/resume  
— 32-pin TSOP  
— Supports reading data from a sector not being  
erased  
— 32-pin PDIP  
■ Minimum 100,000 write/erase cycles guaranteed  
■ High performance  
■ Low power consumption  
— 20 mA typical active read current  
— 30 mA typical program/erase current  
— 55 ns maximum access time  
■ Sector erase architecture  
— Uniform sectors of 64 Kbytes each  
■ Enhanced power management for standby  
mode  
— Any combination of sectors can be erased.  
Also supports full chip erase.  
— <1 µA typical standby current  
— Standard access time from standby mode  
■ Sector protection  
— Hardware method that disables any combination  
of sectors from write or erase operations  
GENERAL DESCRIPTION  
The Am29F040 is a 4 Mbit, 5.0 Volt-only Flash memory  
organized as 512 Kbytes of 8 bits each. The Am29F040  
is offered in a 32-pin package. This device is designed  
to be programmed in-system with the standard system  
which controls the erase and programming circuitry.  
Write cycles also internally latch addresses and data  
needed for the programming and erase operations.  
Reading data out of the device is similar to reading  
from 12.0 Volt Flash or EPROM devices.  
5.0 V V  
supply. A 12.0 V V  
is not required for  
CC  
PP  
write or erase operations. The device can also be  
reprogrammed in standard EPROM programmers.  
The Am29F040 is programmed by executing the pro-  
gram command sequence. This will invoke the Embed-  
ded Program Algorithm which is an internal algorithm  
that automatically times the program pulse widths and  
verifies proper cell margin. Typically, each sector can  
be programmed and verified in less than one second.  
Erase is accomplished by executing the erase com-  
mand sequence. This will invoke the Embedded Erase  
Algorithm which is an internal algorithm that automati-  
cally preprograms the array if it is not already pro-  
grammed before executing the erase operation. During  
erase, the device automatically times the erase pulse  
widths and verifies proper cell margin.  
The standard Am29F040 offers access times between  
55 ns and 150 ns, allowing operation of high-speed  
microprocessors without wait states. To eliminate bus  
contention the device has separate chip enable (CE),  
write enable (WE) and output enable (OE) controls.  
The Am29F040 is entirely command set compatible  
with the JEDEC single-power-supply Flash standard.  
Commands are written to the command register using  
standard microprocessor write timings. Register con-  
tents serve as input to an internal state machine  
Publication# 17113 Rev: E Amendment/0  
Issue Date: November 1996  
1234567...33

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