Datasheet > AM27C020-55DC500

AM27C020-55DC500

更新时间： 2024-01-23 01:38:50

品牌	Logo	应用领域
三星 - SAMSUNG		可编程只读存储器内存集成电路
页数	文件大小	规格书
43页	1145K
描述
UVPROM, 512MX8, 25ns, CMOS, PBGA52, 12 X 17 MM, 1 MM PITCH, LEAD FREE, ULGA-52

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AM27C020-55DC500 技术参数

生命周期：	Obsolete	零件包装代码：	LGA
包装说明：	VFLGA,	针数：	52
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.61	风险等级：	5.84
最长访问时间：	25 ns	JESD-30 代码：	R-PBGA-B52
长度：	17 mm	内存密度：	4294967296 bit
内存集成电路类型：	UVPROM	内存宽度：	8
功能数量：	1	端子数量：	52
字数：	536870912 words	字数代码：	512000000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512MX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	VFLGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：	PARALLEL	座面最大高度：	0.65 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BUTT	端子位置：	BOTTOM
宽度：	12 mm	Base Number Matches：	1

AM27C020-55DC500 数据手册

浏览型号AM27C020-55DC500的Datasheet PDF文件第10页

Advance

FLASH MEMORY

K9K8G08U1B

K9F4G08U0B K9F4G08B0B

PIN DESCRIPTION

Pin Name

Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

CLE

ALE

The I/O pins are used to input command, address and data, and to output data during read operations. The I/

O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode in program or erase operation.

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-

age generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

R/B

POWER

Vcc

Vss

N.C

VCC is the power supply for device.

GROUND

NO CONNECTION

Lead is not internally connected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

Samsung Confidential

1...4 5 678 9 10...43

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与AM27C020-55DC500相关器件

型号	品牌	获取价格	描述	数据表
AM27C020-55DC5B	AMD	获取价格	2 Megabit (256 K x 8-Bit) CMOS EPROM
AM27C020-55DCB	ETC	获取价格	x8 EPROM
AM27C020-55DE5	AMD	获取价格	2 Megabit (256 K x 8-Bit) CMOS EPROM
AM27C020-55DE5B	AMD	获取价格	2 Megabit (256 K x 8-Bit) CMOS EPROM
AM27C020-55DI	SPANSION	获取价格	UVPROM, 256KX8, 55ns, CMOS, CDIP32, CERAMIC, DIP-32
AM27C020-55DI5	AMD	获取价格	2 Megabit (256 K x 8-Bit) CMOS EPROM
AM27C020-55DI5B	AMD	获取价格	2 Megabit (256 K x 8-Bit) CMOS EPROM
AM27C020-55DIB	SPANSION	获取价格	UVPROM, 256KX8, 55ns, CMOS, CDIP32, CERAMIC, DIP-32
AM27C020-55EC	ETC	获取价格	x8 EPROM
AM27C020-55EC5	ETC	获取价格	x8 EPROM

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