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Alaska C 9340P PDF预览

Alaska C 9340P

更新时间: 2024-11-21 17:02:15
品牌 Logo 应用领域
迈威 - MARVELL /
页数 文件大小 规格书
2页 83K
描述
Dual 800GbE Retimer DSP PSM-4, Gearbox, MACsec and PTP Ethernet PHY with 100G serial I/Os at 1.6T capacity

Alaska C 9340P 数据手册

 浏览型号Alaska C 9340P的Datasheet PDF文件第2页 
Product Brief  
Marvell® Alaska® C MV-CHX9340P  
Dual 800G, Quad 400G, Octal 200G, 16 port 100G Ethernet Transceiver with MACsec  
and Class C PTP  
Overview  
The Marvell® Alaska® C MV-CHX9340P is the industry’s highest-  
performance and lowest-power single-chip 800 GbE PAM4 PHY  
transceiver capable of driving eight lanes of 106 Gbps PAM4 to  
support SR, DR, FR and LR optical links. The device performs  
IEEE 802.1AE MACsec encryption functionality for two ports of  
800 GbE, four ports of 400 GbE, eight ports of 200 GbE or  
sixteen ports of 100 GbE. It also supports Class C PTP  
timestamping functionality as defined by IEEE 1588 v2  
specifications. The device supports full duplex transmission at  
all supported speeds, over a variety of media including optics,  
passive direct attach (DAC) cables, active electric (AEC) cables  
and backplanes.  
necessary FEC termination and regeneration capabilities for all  
FEC types including Clause-134 RS (544, 514), Clause-91 and  
Clause108 RS (528, 514) RS-FEC, and FC (2212, 2080) FEC.  
The MV-CHX9340P has a fully symmetric architecture supports  
Auto-Negotiation and coefficient training capabilities on both  
host and line interfaces to provide complete system design  
flexibility, the AN/LT implementation is fully compliant to the  
IEEE 802.3 to support operation over KR backplanes and CR  
passive copper cables. The device is designed with a full 16x16  
SerDes crossbar to support port multiplexing applications.  
Internal registers can be accessed via an MDIO/MDC serial  
management interface which is compliant with the IEEE 802.3  
specification (Clause 45).  
The device is targeted to next generation high density  
networking solutions based on 100G serial electrical signaling  
that requires MACsec, IPsec, PTP or Hitless Mux functionalities.  
The device also supports a variety of gearboxing modes to  
translate between 10G/25G NRZ, 50G PAM4 and 100G PAM4  
modes for 800 GbE, 400 GbE, 200 GbE and 100 GbE, with the  
The MV-CHX9340P is packaged in a 27 mm x 27 mm 841-pin  
FCBGA package with 0.9mm ball pitch.  
Block Diagram  
16x100G/50G PAM4 or 25G/10G NRZ  
112G/56G-CR/KR Capable SerDes  
10G/25GbE/50GbE/100GbE/200GbE/  
400GbE/800GbE PCS+ FEC  
2:1 Hitless Mux  
MAC+256 bit MACsec+PTP Time Stamping  
10G/25GbE/50GbE/100GbE/200GbE/  
400GbE/800GbE PCS+FEC  
MDIO  
JTAG  
SyncE  
LED  
Auto-Negotiation  
Coefficient Training  
112G/56G-CR/KR Capable SerDes  
16x100G/50G PAM4 or 25G/10G NRZ  

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