Datasheet > AL1I-67204V-55

AL1I-67204V-55

更新时间： 2024-01-15 00:55:54

品牌	Logo	应用领域
TEMIC		先进先出芯片
页数	文件大小	规格书
16页	145K
描述
FIFO, 4KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AL1I-67204V-55 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.84
最长访问时间：	55 ns	周期时间：	70 ns
JESD-30 代码：	R-GDIP-T28	长度：	37.25 mm
内存密度：	36864 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	4096 words	字数代码：	4000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	4KX9
可输出：	NO	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	5.72 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	NO
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	15.24 mm
Base Number Matches：	1

AL1I-67204V-55 数据手册

MATRA MHS

L 67203/L 67204

2K × 9 & 4K × 9 / 3.3 Volts CMOS Parallel FIFO

Introduction

The L67203/204 implement a first-in first-out algorithm, Using an array of eigh transistors (8 T) memory cell and

featuring asynchronous read/write operations. The FULL fabricated with the state of the art 1.0 µm lithography

and EMPTY flags prevent data overflow and underflow. named SCMOS, the L 67203/204 combine an extremely

The Expansion logic allows unlimited expansion in word low standby supply current (typ = 1.0 µA) with a fast

size and depth with no timing penalties. Twin address access time at 55 ns over the full temperature range. All

pointers automatically generate internal read and write versions offer battery backup data retention capability

addresses, and no external address information are with a typical power consumption at less than 5 µW.

required for the MHS FIFOs. Address pointers are

For military/space applications that demand superior

automatically incremented with the write pin and read

levels of performance and reliability the L 67203/204 is

pin. The 9 bits wide data are used in data communications

processed according to the methods of the latest revision

applications where a parity bit for error checking is

of the MIL STD 883 (class B or S) and/or ESA SCC 9000.

necessary. The Retransmit pin resets the Read pointer to

zero without affecting the write pointer. This is very

useful for retransmitting data when an error is detected in

the system.

Features

D First-in first-out dual port memory

D Single supply 3.3 ± 0.3 volts

D 2048 × 9 organisation (L 67203)

D 4096 × 9 organisation (L 67204)

D Fast access time

D Fully expandable by word width or depth

D Asynchronous read/write operations

D Empty, full and half flags in single device mode

D Retransmit capability

D Bi-directional applications

Commercial, industrial automotive and military :

55, 60, 65 ns

D Battery back-up operation 2 V data retention

D TTL compatible

D Wide temperature range : – 55 °C to + 125 °C

D High performance SCMOS technology

D 67203L/204L low power

67203V/204V very low power

Rev. C (10/11/94)

12 3 4 5 6 7...16

下载PDF

与AL1I-67204V-55相关器件

型号	品牌	描述	获取价格	数据表
AL1I-67204V-60	TEMIC	FIFO, 4KX9, 60ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67204V-65	ATMEL	FIFO, 4KX9, 65ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-55	TEMIC	FIFO, 8KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-60	TEMIC	FIFO, 8KX9, 60ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-65	TEMIC	FIFO, 8KX9, 65ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205V-55	TEMIC	FIFO, 8KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

AL1I-67204V-55

AL1I-67204V-55 技术参数

AL1I-67204V-55 数据手册

与AL1I-67204V-55相关器件

与AL1I-67204V-55相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AL1I-67204V-55

AL1I-67204V-55 技术参数

AL1I-67204V-55 数据手册

与AL1I-67204V-55相关器件

与AL1I-67204V-55相关文章

您还可以找

您在本页遇到什么问题？