[AK7722]
PIN FUNCTION
No.
1
2
3
4
5
6
7
8
Name
AINL3
I/O
Function
Classification
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Power Supply
Power Supply
ADC1 Lch Single-ended Input 3 Pin.
I
I
I
I
I
I
I
I
I
-
-
ADC1 Inverted Rch Differential Input 2 Pin
ADC1 Non-inverted Rch Differential Input 2 Pin
ADC1 Inverted Lch Differential Input 2 Pin
ADC1 Non-inverted Lch Differential Input 2 Pin
ADC1 Inverted Rch Differential Input 1 Pin
ADC1 Non-inverted Rch Differential Input 1 Pin
ADC1 Inverted Lch Differential Input 1 Pin
ADC1 Non-inverted Lch Differential Input 1 Pin
Analog Power Supply Pin 3.0 ~ 3.6V
AINR2N
AINR2P
AINL2N
AINL2P
AINR1N
AINR1P
AINL1N
AINL1P
9
10 AVDD
11 VSS1
Analog Ground Pin 0V
O R and C Component Connect Pin for PLL
12 LFLT
Refer to “7. LFLT Pin External Connection”. This pin outputs “L” during Analog Output
initial reset.
I
Test 1 Pin (Internal pull-down)
13 TESTI1
Test
This pin must be connected to VSS.
I
I
I
-
-
14 GLRCKI
15 GBICKI
16 SDIN5
17 DVDD
18 VSS2
Frame Clock Input Pin for Voice Guidance
Bit Clock Input Pin for Voice Guidance
Serial Audio Input Pin for Voice Guidance
Digital Power Supply Pin 3.0~3.6V
Ground Pin 0V
Digital Input
Digital Input
Digital Input
Power Supply
Power Supply
Crystal oscillator input pin
19 XTI
I
Clock
Connect a crystal oscillator between this pin and the XTO pin, or input an
external clock to the XTI pin.
Crystal Oscillator Output Pin
When a crystal oscillator is used, connect it between XTI and XTO. When
an external clock is used, leave this pin open. During initial reset, the output
of this pin is not determinable.
20 XTO
O
Clock
Programmable Bit Output Pin
This pin outputs “L” during initial reset.
Conditional Jump Pin0
The conditional jump pin (JX0) is valid by setting control register (JX0E) to
“1”.
21 GP1
22 JX0
O
I
Digital Output
Conditional Input
LR Channel Select Clock Pin 1
LR clock should be input to this pin in slave mode.
Serial Bit Clock Input Pin 1
System Clock
Input
System Clock
Input
23 LRCKI
24 BICKI
I
I
BITCLOCK (48fs or 64fs) should be input to this pin in slave mode.
I
I
Serial Data Input 1 Pin
Serial Data Input 2 Pin
Conditional Jump Pin1
25 SDIN1
SDIN2
Digital Input
Digital Input
26
JX1
I
The conditional jump pin (JX1) is valid by setting control register (JX1E) to Conditional Input
“1”.
System Clock
27 SRLRCK1
28 SRBICK1
I
I
LR Channel Select Clock Pin 1 (for SRC)
Input
System Clock
Serial Bit Clock Input Pin 1 (for SRC)
Input
MS1328-E-00-PB
6
2011/09
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
