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AHE2815DF/HBPBF PDF预览

AHE2815DF/HBPBF

更新时间: 2022-12-01 20:18:51
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
10页 153K
描述
DC-DC Regulated Power Supply Module, 2 Output, 15W, Hybrid, FM-10

AHE2815DF/HBPBF 数据手册

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AHE28XXD Series  
AHE2805D  
Table I. Electrical Performance Characteristics - continued  
Test  
Symbol  
Conditions  
Group A  
Subgroups  
Device  
Types  
Limits  
Unit  
-55° Tc +125°C  
Vin = 28 Vdc ±5%, CL= 0  
unless otherwise  
specified  
Min  
Max  
70  
Recovery time step  
transient load  
TTLOAD  
50% load to/from 100%  
load  
4
All  
changes 1, 7  
µs  
5,6  
100  
No load to 50% load  
50% load to no load  
Input step 17 to 40V dc  
4,5,6  
4,5,6  
4,5,6  
All  
All  
All  
1500  
5.0  
1200  
ms  
mVpk  
Output response  
transient step line  
changes 5, 12  
VOTLINE  
Input step 40 to 17V dc  
Input step 17 to 40V dc  
4,5,6  
4,5,6  
All  
All  
-1500  
4.0  
Recovery time  
transient step  
TTLINE  
ms  
line changes1, 5, 12  
Input step 40 to 17V dc  
4,5,6  
4,5,6  
4,5,6  
All  
All  
All  
4.0  
600  
10  
Turn on overshoot 9  
Turn on delay 2, 9  
VTonOS  
TonD  
mVpk  
ms  
I
OUT = 0 and ±625mA  
±
IOUT = 0 and 625mA  
Load fault recovery 12  
TrLF  
4,5,6  
All  
10  
ms  
Notes to Specifications  
1
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±0.1 % of VOUT at 50 % load.  
2
Turn on delay time measurement is for either a step application of power at the input or the removal of a ground signal from the  
inhibit pin (pin 2) while power is applied to the input.  
3
An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit  
protection and is the condition of maximum power dissipation.  
4
5
6
Total power at both outputs. For operation at 16V dc input, derate output power by 33 %.  
Input step transition time between 2.0µs and 10µs.  
Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. A capacitive load in excess  
of the maximum limit will not disturb loop stability but may interfere with the operation of the load fault detection circuitry,  
appearing as a short circuit during turn-on.  
7
8
9
Load step transition time between 2.0µs and 10µs.  
Bandwidth guaranteed by design. Tested for 20KHz to 2.0MHz.  
Tested at each output.  
10 When operating with unbalanced loads, at least 25 % of the load must be on the positive output to maintain regulation.  
11 Parameter guaranteed by line and load regulation tests.  
12 Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be  
guaranteed to the limits specified in Table I.  
www.irf.com  
3

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