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AGLN125V2-ZVQG100 PDF预览

AGLN125V2-ZVQG100

更新时间： 2024-11-29 12:42:03
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
150页 7699K
描述
IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology

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中文翻译

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AGLN125V2-ZVQG100 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TFQFP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.58
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
长度：14 mm湿度敏感等级：3
可配置逻辑块数量：3072等效关口数量：125000
端子数量：100最高工作温度：70 °C
最低工作温度：-20 °C组织：3072 CLBS, 125000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：1.575 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

AGLN125V2-ZVQG100 数据手册

 浏览型号AGLN125V2-ZVQG100的Datasheet PDF文件第2页浏览型号AGLN125V2-ZVQG100的Datasheet PDF文件第3页浏览型号AGLN125V2-ZVQG100的Datasheet PDF文件第4页浏览型号AGLN125V2-ZVQG100的Datasheet PDF文件第5页浏览型号AGLN125V2-ZVQG100的Datasheet PDF文件第6页浏览型号AGLN125V2-ZVQG100的Datasheet PDF文件第7页 
Revision 17  
IGLOO nano Low Power Flash FPGAs  
with Flash*Freeze Technology  
High-Performance Routing Hierarchy  
Features and Benefits  
•
Segmented, Hierarchical Routing and Clock Structure  
Low Power  
Advanced I/Os  
•
•
•
•
•
nanoPower Consumption—Industry’s Lowest Power  
1.2 V to 1.5 V Core Voltage Support for Low Power  
Supports Single-Voltage System Operation  
•
•
•
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 4 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS  
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V  
Low Power Active FPGA Operation  
Flash*Freeze Technology Enables Ultra-Low Power  
Consumption while Maintaining FPGA Content  
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode  
•
•
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
Wide Range Power Supply Voltage Support per JESD8-12,  
Allowing I/Os to Operate from 1.14 V to 1.575 V  
I/O Registers on Input, Output, and Enable Paths  
Selectable Schmitt Trigger Inputs  
•
Small Footprint Packages  
•
•
•
•
•
•
•
•
As Small as 3x3 mm in Size  
Wide Range of Features  
Hot-Swappable and Cold-Sparing I/Os  
Programmable Output Slew Rate and Drive Strength  
Weak Pull-Up/-Down  
•
•
•
10,000 to 250,000 System Gates  
Up to 36 kbits of True Dual-Port SRAM  
Up to 71 User I/Os  
IEEE 1149.1 (JTAG) Boundary Scan Test  
®
Pin-Compatible Packages across the IGLOO Family  
Reprogrammable Flash Technology  
Clock Conditioning Circuit (CCC) and PLL†  
•
•
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process  
Instant On Level 0 Support  
Up to Six CCC Blocks, One with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay  
Capabilities, and External Feedback  
Single-Chip Solution  
Retains Programmed Design When Powered Off  
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System  
Performance  
•
Wide Input Frequency Range (1.5 MHz up to 250 MHz)  
Embedded Memory  
In-System Programming (ISP) and Security  
•
•
1 kbit of FlashROM User Nonvolatile Memory  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
(AES) Decryption via JTAG (IEEE 1532–compliant)  
†
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)  
True Dual-Port SRAM (except × 18 organization)  
†
®
•
•
•
FlashLock Designed to Secure FPGA Contents  
1.2 V Programming  
Enhanced Commercial Temperature Range  
•
Tj = -20°C to +85°C  
AGLN010 AGLN0151 AGLN020  
AGLN060  
AGLN125  
AGLN250  
IGLOO nano Devices  
IGLOO nano-Z Devices  
System Gates  
1
AGLN030Z1 AGLN060Z1 AGLN125Z1 AGLN250Z1  
10,000  
15,000  
20,000  
30,000  
60,000  
512  
1,536  
10  
125,000  
250,000  
Typical Equivalent Macrocells  
VersaTiles (D-flip-flops)  
86  
260  
2
128  
384  
4
172  
520  
4
256  
768  
5
1,024  
3,072  
16  
36  
8
2,048  
6,144  
24  
36  
8
Flash*Freeze Mode (typical, µW)  
2
RAM Kbits (1,024 bits)  
–
–
–
–
18  
2
4,608-Bit Blocks  
–
–
–
–
4
FlashROM Kbits (1,024 bits)  
1
1
1
1
1
1
1
2
Secure (AES) ISP  
–
–
–
–
Yes  
1
Yes  
1
Yes  
1
2,3  
Integrated PLL in CCCs  
–
–
–
–
VersaNet Globals  
4
4
4
6
18  
18  
2
18  
4
I/O Banks  
2
3
3
2
2
Maximum User I/Os (packaged device)  
Maximum User I/Os (Known Good Die)  
34  
34  
49  
–
52  
52  
77  
83  
71  
71  
71  
68  
68  
71  
Package Pins  
UC/CS  
UC36  
QN48  
UC81,  
CS81  
QN68  
UC81, CS81  
QN48, QN68  
VQ100  
CS81  
CS81  
CS81  
QFN  
VQFP  
QN68  
VQ100  
VQ100  
VQ100  
Notes:  
1. Not recommended for new designs.  
2. AGLN030 and smaller devices do not support this feature.  
3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.  
4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe datasheets.  
† AGLN030 and smaller devices do not support this feature.  
June 2013  
I
© 2013 Microsemi Corporation  
1234567...150

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