Revision 4
Fusion Family of Mixed Signal FPGAs
In-System Programming (ISP) and Security
Features and Benefits
•
•
ISP with 128-Bit AES via JTAG
®
High-Performance Reprogrammable Flash Technology
FlashLock Designed to Protect FPGA Contents
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Instant On Single-Chip Solution
Advanced Digital I/O
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS
– Built-In I/O Registers
– 700 Mbps DDR Operation
Hot-Swappable I/Os
350 MHz System Performance
Embedded Flash Memory
•
User Flash Memory – 2 Mbits to 8 Mbits
– Configurable 8-, 16-, or 32-Bit Datapath
– 10 ns Access in Read-Ahead Mode
1 Kbit of Additional FlashROM
•
•
•
•
Integrated A/D Converter (ADC) and Analog I/O
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
Pin-Compatible Packages across the Fusion Family
•
•
•
•
•
•
Up to 12-Bit Resolution and up to 600 Ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: –10.5 V to +12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
– P- and N-Channel Power MOSFET Support
– Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths
ADC Accuracy is Better than 1%
®
•
SRAMs and FIFOs
•
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
•
•
True Dual-Port SRAM (except ×18)
Programmable Embedded FIFO Control Logic
•
Soft ARM Cortex-M1 Fusion Devices (M1)
®
On-Chip Clocking Support
•
ARM Cortex-™M1–Enabled
•
•
•
•
Internal 100 MHz RC Oscillator (accurate to 1%)
Crystal Oscillator Support (32 KHz to 20 MHz)
Pigeon Point ATCA IP Support (P1)
®
•
Targeted to Pigeon Point Board Management Reference
(BMR) Starter Kits
Designed in Partnership with Pigeon Point Systems
ARM Cortex-M1 Enabled
Programmable Real-Time Counter (RTC)
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
•
•
MicroBlade Advanced Mezzanine Card Support (U1)
Low Power Consumption
•
•
•
•
•
Targeted to Advanced Mezzanine Card (AdvancedMC™ Designs)
Designed in Partnership with MicroBlade
8051-Based Module Management Controller (MMC)
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low-Power Modes
Table 1 • Fusion Family
Fusion Devices
AFS090
AFS250
AFS600
AFS1500
*
ARM Cortex-M1 Devices
M1AFS250
M1AFS600
M1AFS1500
Pigeon Point Devices
MicroBlade Devices
P1AFS600
P1AFS1500
U1AFS250
U1AFS600
U1AFS1500
System Gates
90,000
2,304
Yes
1
250,000
600,000
13,824
Yes
2
1,500,000
38,400
Yes
2
Tiles (D-flip-flops)
Secure (AES) ISP
PLLs
6,144
Yes
1
General
Information
Globals
18
18
1
18
18
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
FlashROM Bits
1
2
4
2M
1,024
6
2M
1,024
8
4M
1,024
24
8M
Memory
1,024
60
RAM Blocks (4,608 bits)
RAM kbits
27
36
6
108
10
270
10
Analog Quads
5
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
15
18
6
30
30
5
10
10
Analog and I/Os
4
4
5
5
75
114
24
172
40
252
40
20
Note: *Refer to the Cortex-M1 product brief for more information.
January 2013
I
© 2013 Microsemi Corporation
5秒后页面跳转
解析光耦仿真器：升级光耦合器技术的必要性
英伟达新一代Blackwell GPU过热问题致交付延迟
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
