Datasheet > AFE1205

AFE1205

更新时间： 2024-01-12 11:06:34

品牌	Logo	应用领域
BB		/
页数	文件大小	规格书
10页	199K
描述
2Mbps, Single Pair HDSL ANALOG FRONT END

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技术参数
数据手册

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AFE1205 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SSOP, SSOP48,.4	Reach Compliance Code：	unknown
风险等级：	5.9	数据速率：	2320 Mbps
JESD-30 代码：	R-PDSO-G48	JESD-609代码：	e0
长度：	15.875 mm	湿度敏感等级：	2
功能数量：	1	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP48,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3,5 V	认证状态：	Not Qualified
座面最大高度：	2.79 mm	子类别：	Other Telecom ICs
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	DIGITAL SLIC
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm	Base Number Matches：	1

AFE1205 数据手册

The PLL section of the AFE1205 should be decoupled with

both a 10µF tantalum capacitor and a 0.1µF ceramic capaci-

tor. Both capacitors should be placed between pins 1 and 2.

The ceramic capacitor should be placed as close to the

AFE1205 as possible. The placement of the tantalum capaci-

tor is not as critical, but should be close. A 5Ω to 10Ω

resistor should be used to connect the PLL supply (pin 2) to

the analog supply. This resistor, in combination with the

10µF tantalum capacitor, form a low pass filter to keep

LAYOUT

The analog front end of an HDSL system has a number of

conflicting requirements. It must accept and deliver digital

outputs at fairly high rates of speed, phase-lock to a high-

speed digital clock, and convert the line input to a high-

precision (14-bit) digital output. Thus, there are really three

sections of the AFE1205: the digital section, the phase-

locked loop, and the analog section. A combined analog and

digital ground plane is recommended. The ground plane

should pass under all of the AFE1205 and its pins.

glitches that occur on the general analog supply, AV_DD

from affecting the PLL supply. The PLL ground (pin 1)

should connect directly to the grond plane.

The power supply for the digital section of the AFE1205 can

range from 3.3V to 5V. This supply should be decoupled to

digital ground with a ceramic 0.1µF capacitor placed as

close to DGND (pin 12) and DV_DD(pin 13) as possible.

Ideally, both a digital power supply plane and a ground

plane should run up to and underneath the digital pins of the

AFE1205 (pins 3 through 26). However, DV_DDmay be

supplied by a wide printed circuit board (PCB) trace. A

ground plane underneath all digital pins is strongly recom-

mended.

The remaining portion of the AFE1205 should be considered

analog. All AGND pins should be connected directly to a

common analog ground plane and all AV_DDpins should be

connected to an analog 5V power plane. Both of these planes

should have a low impedance path to the power supply.

Ideally, all ground planes and traces and all power planes

and traces should return to the power supply connector

before being connected together (if necessary). Each ground

and power pair should be routed over each other, should not

overlap any portion of another pair, and the pairs should be

separated by a distance of at least 0.25 inch (6mm). One

exception is that the digital and analog ground planes should

be connected together underneath the AFE1205 by a small

trace.

The Phase Locked Loop (PLL) analog supply, pin 2, must be

derived from AV_DD, the general analog supply. The power

supply to the PLL must be in the range of 4.75V to 5.25V.

AFE1205

1...7 8 910

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与AFE1205相关器件

型号	品牌	获取价格	描述	数据表
AFE1205E	BB	获取价格	2Mbps, Single Pair HDSL ANALOG FRONT END
AFE1205E/1KG4	TI	获取价格	IC,XDSL INTERFACE,HDSL,ANALOG FRONT END,CMOS,SSOP,48PIN,PLASTIC
AFE1224	BB	获取价格	2Mbps, Single Pair ANALOG FRONT END
AFE1224	TI	获取价格	2Mbps, Single Pair ANALOG FRONT END
AFE1224E	BB	获取价格	2Mbps, Single Pair ANALOG FRONT END
AFE1224E/1K	ETC	获取价格	xDSL Interface
AFE1224E-2/1K	TI	获取价格	2Mbps, Single Pair ANALOG FRONT END
AFE1224E-2/1K	ROCHESTER	获取价格	DATACOM, DIGITAL SLIC, PDSO28, SSOP-28
AFE1224E-2/1KG4	TI	获取价格	2Mbps, Single Pair Analog Front End 28-SSOP
AFE1230	BB	获取价格	G.SHDSL ANALOG FRONT-END

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