PRELIMINARY TECHNICAL DATA
ANALOG
JPEG2000 Co-processor
ADV-JP2000
DEVICES
Preliminary Technical Data
16-May-2001
Features
General Description
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SURF™ (Spatial Ultra-efficient Recursive Filtering)
patented technology enables high-performance,
low-power, and low-cost JPEG2000 compression/
decompression.
Lossless compression at >10 Mpixels/second
Reversible and irreversible 5/3 wavelet transform.
Lossless and Lossy compression modes. Supports
8 or 10-bit pixel components in reversible mode and
8 to 14-bit pixel components in irreversible mode.
Programmable tile size up to 160 x 128 in three-
component interleaved mode, up to 256 x 256 in
single-component mode.
Flexible pixel/component interface.
Coding pass distortion metrics provided for precise
control of compressed image size.
A single 16-bit asynchronous SRAM style interface
allows glue-less connection to most microcontrollers
and ASICs.
The ADV-JP2000 is a high-performance image com-
pression co-processor that implements the computa-
tionally intensive operations of the JPEG2000 (J2K)
image compression standard. The ADV-JP2000 can
process images at a rate of >10 Mpixels/sec in lossless
mode, and at significantly higher rates when used in
lossy mode. The chip supports lossless compression
of 8 or 10-bit component data and can support lossy
compression of component data up to 14-bits. This
chip, along with a minimal amount of software on the
user’s host processor, will provide a complete high per-
formance JPEG2000 image compression and decom-
pression solution. The chip contains a full custom
wavelet processor and entropy codec as well as asso-
ciated interface and control functions. The wavelet
processor implements the 5/3 wavelet transform in
either reversible or irreversible modes. The entropy
codec supports the key features in the current
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JPEG2000 specification. The ADV-JP2000 provides a
very flexible interface that supports a wide variety of
pixel and component formats.
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3.3v I/O and 1.5-1.8v core supply.
7mm x 7mm 48-ball fpBGA.
The ADV-JP2000 provides a single simple asynchro-
nous interface for all communications between itself
and a host CPU or system ASIC. The ADV-JP2000
supports both single and dual-address DMA transfers
to and from on-chip FIFOs. A complete definition of the
DMA process is described in “DMA Access Modes,” on
page 5. Control and status registers within the ADV-
JP2000 are addressed directly using the address bus,
Applications
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Digital Still Cameras
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Video editing systems
Wavelet Pipe &
DATA
Data FIFO
Quantizer
ADDR
CTRL
Control & Status
Attribute FIFO
SRAM
STATUS
Entropy CODEC
CLKIN
PLL
Rev. PrA
SURF is a trademark of Analog Devices, Inc.
This information applies to a product under development. Its characteristics and specifications are subject to change without no tice. Analog Devices assumes no obligation
regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights
of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:1-800-ANALOGD (262-5643) Fax:781-461-3700
www.analog.com/video
©Analog Devices,Inc., 2001
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