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ADuM6411BRSZ-RL7 PDF预览

ADuM6411BRSZ-RL7

更新时间： 2024-02-01 16:03:56
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
29页 874K
描述
Quad-Channel Isolators with Integrated DC-to-DC Converters

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ADuM6411BRSZ-RL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：SSOP,
针数：24Reach Compliance Code：compliant
风险等级：5.59其他特性：ALSO REQUIRE PRIMARY SUPPLY VOLTAGE (VDDP) RANGES FROM 3V TO 5.5V
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：8.2 mm
湿度敏感等级：3功能数量：1
端子数量：24最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
座面最大高度：2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：5.3 mm
Base Number Matches：1

ADuM6411BRSZ-RL7 数据手册

 浏览型号ADuM6411BRSZ-RL7的Datasheet PDF文件第23页浏览型号ADuM6411BRSZ-RL7的Datasheet PDF文件第24页浏览型号ADuM6411BRSZ-RL7的Datasheet PDF文件第25页浏览型号ADuM6411BRSZ-RL7的Datasheet PDF文件第27页浏览型号ADuM6411BRSZ-RL7的Datasheet PDF文件第28页浏览型号ADuM6411BRSZ-RL7的Datasheet PDF文件第29页 
ADuM6410/ADuM6411/ADuM6412  
Data Sheet  
APPLICATIONS INFORMATION  
To reduce the level of electromagnetic radiation, the impedance  
to high frequency currents between the VISO and GNDISO pins  
and the PCB trace connections can be increased. Using this  
method of EMI suppression controls the radiating signal at its  
source by placing surface-mount ferrite beads in series with the  
PCB LAYOUT  
The ADuM6410/ADuM6411/ADuM6412 digital isolators with  
0.15 W isoPower integrated dc-to-dc converters require no  
external interface circuitry for the logic interfaces. Power supply  
bypassing is required at the input and output supply pins (see  
Figure 32). Note that low ESR bypass capacitors of 0.01 µF to  
0.1 µF value are required between the VDD1 pin and GND1 pin,  
and between the VDD2 pin and GNDISO pin, as close to the chip  
pads as possible, for proper operation of the data channels. The  
isoPower inputs require several passive components to bypass  
the power effectively as well as set the output voltage and bypass  
the core voltage regulator (see Figure 30 through Figure 32).  
V
ISO and GNDISO pins, as seen in Figure 32. The impedance of  
the ferrite bead is chosen to be about 2 kΩ between the 100  
MHz and 1 GHz frequency range, to reduce the emissions at the  
125 MHz primary switching frequency and the 250 MHz  
secondary side rectifying frequency and harmonics. See Table  
33 for examples of appropriate surface-mount ferrite beads. For  
additional reduction in emissions, PCB stitching capacitance  
can be implemented with a high voltage SMT safety capacitor.  
For optimal performance, it is important that the capacitor is  
connected directly between GND1 (Pin 12) and GNDISO (Pin 13),  
as shown in Figure 32. This capacitor is a SMT Size 1812, has a  
3 kV voltage rating, and is manufactured by TDK Corporation  
(C4532C0G3F101K160KA).  
PDIS  
10  
V
DDP  
11  
12  
GND  
1
+
10µF  
0.1µF  
Figure 30. VDDP Bias and Bypass Components  
Table 33. Surface-Mount Ferrite Beads Example  
V
V
SEL  
R2  
15  
14  
13  
Manufacturer  
Taiyo Yuden  
Part No.  
BKH1005LM182-T  
BLM15HD182SN1  
30kΩ  
FB1  
ISO  
VISO OUT  
GND  
ISO  
Murata Electronics  
0.1µF  
10µF  
FB2  
R1  
10kΩ  
ISO GND  
V
V
DD1  
DD2  
0.1µF  
0.1µF  
GND  
1
GND  
ISO  
Figure 31. VISO Bias and Bypass Components  
V
V
V
V
/V  
V
V
V
V
V
/V  
IA OA  
OA IA  
/V  
/V  
The power supply section of the ADuM6410/ADuM6411/  
ADuM6412 uses a 125 MHz oscillator frequency to efficiently  
pass power through its chip-scale transformers. Bypass capacitors  
are required for several operating frequencies. Noise suppression  
requires a low inductance, high frequency capacitor; ripple  
suppression and proper regulation require a large value capacitor.  
These capacitors are most conveniently connected between the  
IB OB  
OB IB  
/V  
/V  
IC OC  
OC IC  
ADuM6410/  
ADuM6411/  
ADuM6412  
/V  
/V  
ID OD  
OD ID  
V
E1  
E2  
NIC  
NIC  
GND  
1
GND  
ISO  
PDIS  
V
SEL  
ISO  
V
V
DDP  
GND  
1
GND  
ISO  
V
DDP pin and GND1 pin, and between the VISO pin and GNDISO pin.  
10µF 0.1µF  
0.1µF FERRITES 10µF  
To suppress noise and reduce ripple, a parallel combination of at least  
two capacitors is required. The recommended capacitor values are  
0.1 µF and 10 µF for VDD1. The smaller capacitor must have a low  
ESR; for example, use of a ceramic capacitor is advised. Note that  
the total lead length between the ends of the low ESR capacitor  
and the input power supply pin must not exceed 2 mm. Installing  
the bypass capacitor with traces more than 2 mm in length may  
result in data corruption.  
SMT 100pF SAFETY CAPACITOR  
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.  
Figure 32. Recommended PCB Layout  
In applications involving high common-mode transients, ensure  
that board coupling across the isolation barrier is minimized.  
Furthermore, design the board layout such that any coupling  
that does occur equally affects all pins on a given component  
side. Failure to ensure these steps can cause voltage differentials  
between pins, exceeding the absolute maximum ratings specified in  
Table 26, thereby leading to latch-up and/or permanent damage.  
Rev. 0 | Page 26 of 29  
 
 
 
 
 
 
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