Data Sheet
ADuM6410/ADuM6411/ADuM6412
THEORY OF OPERATION
The dc-to-dc converter section of the ADuM6410/ADuM6411/
ADuM6412 works on principles that are common to most
modern power supplies. It has a split controller architecture with
isolated PWM feedback. VDDP power is supplied to an oscillating
circuit that switches current into a chip-scale air core transformer.
Power transferred to the secondary side is rectified and regulated to
a value between 3.15 V and 5.25 V, depending on the setpoint
supplied by an external voltage divider (see Equation 1). The
secondary (VISO) side controller regulates the output by creating a
PWM control signal that is sent to the primary (VDDP) side by a
dedicated iCoupler data channel. The PWM modulates the oscilla-
tor circuit to control the power being sent to the secondary side.
Feedback allows for significantly higher power and efficiency.
less than 80% duty factor, leaving no margin to support load or
temperature variations.
Typically, the ADuM6410/ADuM6411/ADuM6412 dissipate
about 17% more power between room temperature and maxi-
mum temperature; therefore, the 20% PWM margin covers
temperature variations.
The ADuM6410/ADuM6411/ADuM6412 implement
undervoltage lockout (UVLO) with hysteresis on the primary
and secondary side input/output pins as well as the VDDP power
input. This feature ensures that the converter does not go into
oscillation due to noisy input power or slow power-on ramp rates.
The digital isolator channels use a high frequency carrier to
transmit data across the isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide isolation.
Using an on/off keying (OOK) technique and the differential
architecture shown in Figure 29, the digital isolator channels have
very low propagation delay and high speed. Internal regulators and
input/output design techniques allow logic and supply voltages over
a wide range from 1.7 V to 5.5 V, offering voltage translation of
1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed for
high common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and
other techniques.
(R1 R2)
VISO 1.225 V
(1)
R1
where:
R1 is a resistor between VSEL and GNDISO
R2 is a resistor between VSEL and VISO
.
.
Because the output voltage can be adjusted continuously
there are an infinite number of operating conditions. This
data sheet addresses three discrete operating conditions in the
Specifications section. Many other combinations of input and
output voltage are possible; Figure 15 shows the supported
voltage combinations at room temperature. Figure 15 was
generated by fixing the VISO load and decreasing the input
voltage until the PWM was at 80% duty cycle. Each of the figures
represents the minimum input voltage that is required for
operation under this criterion. For example, if the application
requires 30 mA of output current at 5 V, the minimum input
Figure 29 shows the waveforms of the digital isolator channels
that have the condition of the fail-safe output state equal to low,
where the carrier waveform is off when the input state is low. If
the input side is off or not operating, the low fail-safe output state
sets the output to low.
voltage at VDDP is 4.25 V. Figure 15 also illustrates why the VDDP
=
3.3 V input and VISO = 5 V configuration is not recommended.
Even at 10 mA of output current, the PWM cannot maintain
REGULATOR
REGULATOR
RECEIVER
TRANSMITTER
V
V
OUT
IN
GND
GND
2
1
Figure 29. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
Rev. 0 | Page 25 of 29