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ADUM5202CRWZ2

更新时间： 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
23页 501K
描述
Dual-Channel Isolators with Integrated DC/DC Converter

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ADUM5202CRWZ2 数据手册

 浏览型号ADUM5202CRWZ2的Datasheet PDF文件第1页浏览型号ADUM5202CRWZ2的Datasheet PDF文件第2页浏览型号ADUM5202CRWZ2的Datasheet PDF文件第4页浏览型号ADUM5202CRWZ2的Datasheet PDF文件第5页浏览型号ADUM5202CRWZ2的Datasheet PDF文件第6页浏览型号ADUM5202CRWZ2的Datasheet PDF文件第7页 
Preliminary Technical Data  
SPECIFICATIONS  
ADuM5200/5201/5202  
ELECTRICAL CHARACTERISTICS – 5V PRIMARY INPUT SUPPLY / 5V SECONDARY ISOLATED SUPPLY1  
4.5 V ≤ VDD1 ≤ 5.5 V, VSEL=VISO; all voltages are relative to their respective ground. All min/max specifications apply over the entire  
recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD = 5.0 V, VISO = 5.0 V, VSEL= VISO  
.
Table 1.  
Parameter  
Symbol  
VISO  
VISO(LINE)  
VISO(LOAD)  
VISO(RIP)  
Min  
Typ  
5.0  
1
1
75  
Max  
Unit  
V
mV/V  
%
Test Conditions  
Setpoint  
4.7  
5.4  
IISO=0mA  
IISO=50mA, VDD1=4.5V to 5.5V  
IISO = 10mA to 90mA  
Line Regulation  
Load Regulation  
Output Ripple  
5
mVP-P  
20MHz Bandwidth, CBO=0.1μF ║ 10μF,  
ISO = 100mA  
20MHz Bandwidth, CBO=0.1μF ║ 10μF,  
ISO = 100mA  
I
Output Noise  
VISO(N)  
200  
mVP-P  
I
Switching Frequency  
PWM Frequency  
fOSC  
fPWM  
180  
625  
MHz  
kHz  
DC to 2 Mbps Data Rate2  
Maximum Output Supply Current3  
Efficiency At Max. Output Supply Current4  
IDD1 Supply Current, No VISO load5  
25 Mbps Data Rate (CRWZ Grade Only)  
IDD1 Supply Current, No VISO Load6  
ADuM5200  
IISO(max)  
IDD1(Q)  
100  
mA  
%
f ≤ 1 MHz, VISO=5V  
34  
19  
IISO = IISO(2,max), f ≤ 1 MHz  
IISO = 0mA, f ≤ 1 MHz  
30  
mA  
IDD1(D)  
IDD1(D)  
IDD1(D)  
34  
38  
41  
mA  
mA  
mA  
IISO = 0mA, CL=15pF, f = 12.5 MHz  
IISO = 0mA, CL=15pF, f = 12.5 MHz  
IISO = 0mA, CL=15pF, f = 12.5 MHz  
ADuM5201  
ADuM5202  
Available VISO Supply Current7  
ADuM5200  
IISO(LOAD)  
IISO(LOAD)  
IISO(LOAD)  
IDD1(Max)  
94  
mA  
mA  
mA  
mA  
CL=15pF, f = 12.5 MHz  
CL=15pF, f = 12.5 MHz  
CL=15pF, f = 12.5 MHz  
CL=0pF, f = 0 MHz, VDD = 5V  
ADuM5201  
92  
ADuM5202  
IDD1 Supply Current, Full VISO load8  
90  
290  
I
ISO=100mA  
I/O Input Currents  
IIA, IIB  
VIH  
VIL  
−10  
0.7 VISO  
+0.01  
+10  
μA  
V
V
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
0.3 VISO  
VDD1 − 0.3,  
VISO − 0.3  
VDD1 − 0.3,  
VISO − 0.3  
VOAH, VOBH  
5.0  
4.8  
V
IOx = −20 μA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
VOAH, VOBH  
V
Logic Low Output Voltages  
VOAL, VOBL  
VOAL, VOBL  
0.0  
0.0  
0.1  
0.4  
V
V
IOx = 20 μA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
AC SPECIFICATIONS  
ADuM520xARWZ  
Minimum Pulse Width9  
Maximum Data Rate10  
PW  
1000  
ns  
Mbps  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
1
Propagation Delay11  
tPHL, tPLH  
PWD  
tPSK  
55  
100  
40  
50  
11  
Pulse-Width Distortion, |tPLH − tPHL  
Propagation Delay Skew12  
Channel-to-Channel Matching13  
ADuM520xCRWZ  
|
tPSKCD/OD  
50  
ns  
Minimum Pulse Width9  
Maximum Data Rate14  
Propagation Delay15  
PW  
40  
60  
ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
25  
tPHL, tPLH  
45  
Rev. PrA | Page 3 of 23  
1234567...23

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