ADuM5200/5201/5202
Preliminary Technical Data
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
11
Pulse-Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew16
Channel-to-Channel Matching,
Codirectional Channels17
|
PWD
6
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
5
ps/°C
ns
ns
tPSK
tPSKCD
15
6
Channel-to-Channel Matching,
Opposing-Directional Channels17
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
tPSKCD
15
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD or VISO, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
2.5
35
ns
kV/μs
25
25
|CML|
fr
35
kV/μs
Mbps
VIx = 0 V, V = 1000 V,
transient magnitude = 800 V
Refresh Rate
1.0
1 All voltages are relative to their respective ground.
2 The contributions of supply current values for all four channels are combined at identical data rates.
3 VISO supply current available for external use when all data rates are below 2Mbps. At data rates above 2Mbps data I/O channels will draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the VISO power budget.
4 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of its internal power consumption.
5 IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2Mbps, requiring no
additional dynamic supply current. It reflects the minimum current operating condition.
6 IDD1(D) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum
dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load.
7 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at maximum data rate of 25Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to Power Consumption section for calculation of available current at less than maximum data rate.
8 IDD1(MAX) is the input current under full dynamic and VISO load conditions.
9 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
10 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
11
t
PHL
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
12
t
PSK
is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
13 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
Rev. PrA| Page 4 of 23
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