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ADuM4473CRIZ-RL PDF预览

ADuM4473CRIZ-RL

更新时间: 2024-01-11 11:39:04
品牌 Logo 应用领域
亚德诺 - ADI 稳压器开关
页数 文件大小 规格书
36页 750K
描述
Isolated Switching Regulator with Quad-Channel Isolators

ADuM4473CRIZ-RL 技术参数

Source Url Status Check Date:2013-05-01 14:56:51.07是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.74
其他特性:ALSO WORKS WITH 5 V INPUT;VOUT=(3.3-24 VOLT)模拟集成电路 - 其他类型:SWITCHING REGULATOR
控制技术:PULSE WIDTH MODULATION最大输入电压:3.6 V
最小输入电压:3 V标称输入电压:3.3 V
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:15.3 mm湿度敏感等级:3
功能数量:1端子数量:20
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:2.64 mm子类别:Other Analog ICs
标称供电电压 (Vsup):5 V表面贴装:YES
最大切换频率:515 kHz技术:DMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mm

ADuM4473CRIZ-RL 数据手册

 浏览型号ADuM4473CRIZ-RL的Datasheet PDF文件第28页浏览型号ADuM4473CRIZ-RL的Datasheet PDF文件第29页浏览型号ADuM4473CRIZ-RL的Datasheet PDF文件第30页浏览型号ADuM4473CRIZ-RL的Datasheet PDF文件第32页浏览型号ADuM4473CRIZ-RL的Datasheet PDF文件第33页浏览型号ADuM4473CRIZ-RL的Datasheet PDF文件第34页 
Data Sheet  
ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474  
The preceding magnetic flux density values correspond to specific  
current magnitudes at given distances from the ADuM447x  
transformers. Figure 54 expresses these allowable current magnitudes  
as a function of frequency for selected distances. As shown in  
Figure 54, the ADuM447x are extremely immune and can be  
affected only by extremely large currents operated at a high fre-  
quency that is very close to the component. For the 1 MHz  
example, a 0.5 kA current needs to be placed 5 mm away  
from the ADuM447x to affect component operation.  
1k  
Dynamic I/O current is consumed only when operating a channel  
at speeds higher than the refresh rate of fr. The dynamic current of  
each channel is determined by its data rate. Figure 24 and Figure 28  
show the current for a channel in the forward direction, meaning  
that the input is on the VDDA and VDD2 side of the part. Figure 25  
and Figure 29 show the current for a channel in the reverse  
direction, meaning that the input is on the VISO side of the part.  
Figure 24, Figure 25, Figure 28, or Figure 29 assume a typical  
15 pF output load.  
The following relationship allows the total IDD1 current to be  
DISTANCE = 1m  
IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4  
(5)  
100  
where:  
I
I
DD1 is the total supply input current.  
ISO is the current drawn by the secondary side external load.  
10  
DISTANCE = 100mm  
E is the power supply efficiency at the given output load from  
Figure 17 or Figure 23 at the VISO, VDDA, and VDD2 condition of  
interest.  
1
DISTANCE = 5mm  
I
CHn is the current drawn by a single channel determined from  
0.1  
Figure 24, Figure 25, Figure 28, or Figure 29, depending on  
channel direction.  
0.01  
The maximum external load can be calculated by subtracting  
the dynamic output load from the maximum allowable load.  
1k  
10k  
100k  
1M  
10M  
100M  
MAGNETIC FIELD FREQUENCY (Hz)  
Figure 54. Maximum Allowable Current for Various Current-to-ADuM447x  
Spacings  
I
ISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4  
where:  
ISO (LOAD) is the current available to supply an external secondary  
side load.  
ISO (MAX) is the maximum external secondary side load current  
available at VISO  
ISO (D)n is the dynamic load current drawn from VISO by an  
(6)  
In combinations of strong magnetic field and high frequency,  
any loops formed by PCB traces can induce error voltages that  
are sufficiently large to trigger the thresholds of succeeding cir-  
cuitry. Take care in the layout of such traces to avoid this  
possibility.  
I
I
.
I
POWER CONSUMPTION  
output or input channel, as shown for a single supply in Figure 26  
or Figure 27 or for a double supply in Figure 30 or Figure 31.  
The VDDA power supply input provides power to the iCoupler data  
channels, as well as to the power converter. For this reason, the  
quiescent currents drawn by the data converter and the primary  
and secondary I/O channels cannot be determined separately. All  
of these quiescent power demands have been combined into the  
The preceding analysis assumes a 15 pF capacitive load on each  
data output. If the capacitive load is larger than 15 pF, the additional  
current must be included in the analysis of IDD1 and IISO (LOAD)  
.
IDDA (Q) current, as shown in Figure 55. The total IDD supply current  
is equal to the sum of the quiescent operating current; the dynamic  
current, IDDA (D), demanded by the I/O channels; and any  
external IISO load.  
FEEDBACK  
I
I
DDA (Q)  
DDA (D)  
CONVERTER  
PRIMARY  
CONVERTER  
SECONDARY  
I
ISO  
I
I
ISO (D)  
DDP (D)  
PRIMARY  
DATA I/O  
4-CHANNEL  
SECONDARY  
DATA I/O  
4-CHANNEL  
Figure 55. Power Consumption Within the ADuM447x  
Rev. 0 | Page 31 of 36  
 
 
 

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