Datasheet > ADUM221N1BRWZ

ADUM221N1BRWZ

更新时间： 2024-01-14 11:34:06

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管
页数	文件大小	规格书
23页	571K
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ADUM221N1BRWZ

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ADUM221N1BRWZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	SOP,
针数：	16	Reach Compliance Code：	compliant
风险等级：	2.13	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	10.3 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	座面最大高度：	2.65 mm
最大供电电压 (Vsup)：	5 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.5 mm
Base Number Matches：	1

ADUM221N1BRWZ 数据手册

ADuM220N/ADuM221N/ADuM225N/ADuM226N

Data Sheet

APPLICATIONS INFORMATION

Pulse width distortion is the maximum difference between these

two propagation delay values and is an indication of how

accurately the timing of the input signal is preserved.

PCB LAYOUT

The ADuM220N/ADuM221N/ADuM225N/ADuM226N

digital isolators require no external interface circuitry for the

logic interfaces. Power supply bypassing is strongly recom-

mended at the input and output supply pins (see Figure 19 and

Figure 20). For the ADuM225N/ADuM226N, bypass capacitors

are most conveniently connected between Pin 1 and Pin 4 for

Channel matching is the maximum amount the propagation

delay differs between channels within a single ADuM220N/

ADuM221N/ADuM225N/ADuM226N component.

Propagation delay skew is the maximum amount the propaga-

tion delay differs between multiple ADuM220N/ADuM221N/

ADuM225N/ADuM226N components operating under the

same conditions.

_DD1and between Pin 5 and Pin 8 for V_DD2. For the ADuM220N/

ADuM221N, bypass capacitors are most conveniently con-

nected between Pin 1 and Pin 3 for V_DD1and between Pin 14

and Pin 16 for V_DD2. The recommended bypass capacitor value is

between 0.01 µF and 0.1 µF. The total lead length between both

ends of the capacitor and the input power supply pin must not

exceed 10 mm. For the ADuM220N/ADuM221N, bypassing

between Pin 3 and Pin 7 and between Pin 9 and Pin 14 must

also be considered, unless the ground pair on each package side

are connected close to the package.

JITTER MEASUREMENT

Figure 22 shows the eye diagram for the ADuM220N/

ADuM221N/ADuM225N/ADuM226N. The measurement

was taken using an Agilent 81110A pulse pattern generator at

150 Mbps with pseudorandom bit sequences (PRBS) 2(n − 1),

n = 14, for 5 V supplies. Jitter was measured with the Tektronix

Model 5104B oscilloscope, 1 GHz, 10 GSPS with the DPOJET

jitter and eye diagram analysis tools. The result shows a typical

measurement on the ADuM220N/ADuM221N/ADuM225N/

ADuM226N with 380 ps p-p jitter.

GND

NIC

DD2

DD1

, V

OA IA

IA OA

NIC

GND

NIC

Figure 19. Recommended PCB Layout for ADuM220N/ADuM221N

, V

DD2

DD1

, V

IA OA

OA IA

GND

Figure 20. Recommended PCB Layout for ADuM225N/ADuM226N

In applications involving high common-mode transients, ensure

that board coupling across the isolation barrier is minimized.

Furthermore, design the board layout such that any coupling

that does occur equally affects all pins on a given component

side. Failure to ensure this can cause voltage differentials between

pins exceeding the Absolute Maximum Ratings of the device,

thereby leading to latch-up or permanent damage.

–10

–5

TIME (ns)

Figure 22. ADuM220N/ADuM221N/ADuM225N/ADuM226N Eye Diagram

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of insula-

tion degradation is dependent on the characteristics of the voltage

waveform applied across the insulation as well as on the materials

and material interfaces.

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The propagation

delay to a Logic 0 output may differ from the propagation delay

to a Logic 1 output.

The two types of insulation degradation of primary interest are

breakdown along surfaces exposed to the air and insulation

wear out. Surface breakdown is the phenomenon of surface

tracking, and the primary determinant of surface creepage

requirements in system level standards. Insulation wear out is the

phenomenon where charge injection or displacement currents

inside the insulation material cause long-term insulation

degradation.

INPUT (V

)

50%

t_PLH

t_PHL

OUTPUT (V

)

50%

Figure 21. Propagation Delay Parameters

Rev. A | Page 20 of 23

1...17 18 192021 22 23

中文翻译

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ADUM221N1BRWZ 替代型号

型号	品牌	替代类型	描述	数据表
ADuM221N1BRWZ-RL	ADI	完全替代	5.0 kV RMS Dual Channel Digital Isolators

与ADUM221N1BRWZ相关器件

型号	品牌	获取价格	描述	数据表
ADuM221N1BRWZ-RL	ADI	获取价格	5.0 kV RMS Dual Channel Digital Isolators
ADUM221X	ADI	获取价格	Digital Isolator Product Selection and Resource Guide
ADUM2250	ADI	获取价格	Hot-Swappable, Dual I2C Isolators, 5 kV
ADUM2250_11	ADI	获取价格	Hot-Swappable, Dual I2C Isolators, 5 kV
ADUM2250_15	ADI	获取价格	Hot Swappable, Dual IC Isolators, 5 kV
ADUM2250ARIZ	ADI	获取价格	Hot-Swappable, Dual I2C Isolators, 5 kV
ADUM2250ARIZ-RL	ADI	获取价格	Hot-Swappable, Dual I2C Isolators, 5 kV
ADUM2250ARWZ	ADI	获取价格	Hot-Swappable, Dual I2C Isolators, 5 kV
ADUM2250ARWZ-RL	ADI	获取价格	Hot-Swappable, Dual I2C Isolators, 5 kV
ADUM2250WARWZ	ADI	获取价格	Hot-Swappable Dual I2C® Isolators, 5 kV

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