ADuM141ES
5.0 Burn-In Life Test, and Radiation
5.1.Burn-In Test Circuit, Life Test Circuit
5.1.1.The test conditions and circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the
intent specified in method 1015 test condition D of MIL –STD-883.
5.1.2.HTRB is not applicable for this drawing.
5.2.Radiation Exposure Circuit
5.2.1.The radiation exposure circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing and acquiring activity upon request. Total dose
irradiation testing shall be performed in accordance with MIL-STD-883 method 1019, condition A.
6.0 MIL-PRF-38535 QMLV Exceptions
6.1.Wafer Fabrication
Wafer fabrication occurs at MIL-PRF-38535 QML Class Q certified facility.
6.2.Wafer Lot Acceptance (WLA)
Full WLA per MIL-STD-883 TM 5007 is not available for this product. SEM inspection per MIL-STD-883
TM2018 is not applicable to the ADuM141E1S. The wafer fabrication process is manufactured using
planarized metallization.
6.3.Device contains bi-metallic wire bonds (Gold bond wires on Aluminum die pads).
7.0 Application Notes
OVERVIEW
The ADuM141E1S use a high frequency carrier to transmit data across the isolation barrier using iCoupler chip scale
transformer coils separated by layers of polyimide isolation. Using an on/off keying (OOK) technique and the
differential architecture shown in Figure 4, the ADuM141E1S have very low propagation delay and high speed.
Internal regulators and input/output design techniques allow logic and supply voltages over a wide range from 1.7 V to
5.5 V, offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed for high common-
mode transient immunity and high immunity to electrical noise and magnetic interference. Radiated emissions are
minimized with a spread spectrum OOK carrier and other techniques.
For the ADuM141E1S that have a high fail-safe output state, Figure 4 illustrates the conditions where the carrier
waveform is off when the input state is high. When the input side is off or not operating, the fail-safe output state of
high (ADuM141E1S) sets the output to high.
Figure 4 – Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
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