Data Sheet
ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These
specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 4.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.50 0.53 mA
0.19 0.24 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.6
0.7
2.5 mA
1.0 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
6.5
1.9
8.1 mA
2.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.3
1.0
2.1 mA
1.4 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
5.0
3.4
6.2 mA
4.2 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2 −10
+0.01 +10 μA
V
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH, VEH
VIL, VEL
2.0
0.8
V
V
V
V
V
V
VOAH, VOBH, VOCH VDD1, VDD2 − 0.1 5.0
VDD1, VDD2 − 0.4 4.8
VOAL, VOBL, VOCL
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
0.0
0.1
0.04 0.1
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
Maximum Data Rate3
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay4
tPHL, tPLH
PWD
tPSK
65
4
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM130xWTRWZ
|
40
50
50
ns
ns
ns
tPSKCD/tPSKOD
Minimum Pulse Width2
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
18
Propagation Delay4
tPHL, tPLH
PWD
27
5
32
3
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching, Codirectional
Channels6
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
15
3
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Rev. I | Page 11 of 32