Data Sheet
ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (90)
43
24
57
36
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
IDD2 (90)
16
29
23
37
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2 −10
+0.01
+10 μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIH, VEH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL, VEL
0.8
0.4
V
V
V
V
V
V
V
Logic High Output Voltages
VOAH, VOBH, VOCH (VDD1 or VDD2) − 0.1 (VDD1 or VDD2
)
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
(VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.04
0.2
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
Maximum Data Rate3
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay4
tPHL, tPLH
PWD
70
11
4
40
ns
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM130xBRW
|
ps/°C
ns
ns
tPSK
tPSKCD/tPSKOD
50
50
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
15
tPHL, tPLH
PWD
35
5
50
3
4
ns
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
|
ps/°C
ns
tPSK
6
3
Channel-to-Channel Matching, Codirectional tPSKCD
Channels6
ns
Channel-to-Channel Matching, Opposing-
Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
8.3
120
30
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
tPHL, tPLH
PWD
40
2
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
ps/°C
ns
tPSK
14
2
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD
ns
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
Rev. I | Page 9 of 32