ADT7516/ADT7517/ADT7519
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
V
V
-B
-A
1
2
3
4
5
6
7
8
16
15
V
V
-C
OUT
OUT
-D
OUT
OUT
ADT7516/
ADT7517/
ADT7519
V
-IN
14 AIN4
REF
CS
13 SCL/SCLK
12 SDA/DIN
11 DOUT/ADD
10 INT/INT
TOP VIEW
(Not to Scale)
GND
V
DD
D+/AIN1
D–/AIN2
9
LDAC/AIN3
Figure 7. Pin Configuration (QSOP Package)
Table 5. Pin Function Descriptions
Pin
No.
Mnemonic Description
1
2
3
4
VOUT-B
VOUT-A
VREF-IN
CS
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Reference Input Pin for All Four DACs. This input is buffered and has an input range from 1 V to VDD.
SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables
the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial
clocks. It is recommended that this pin be tied high to VDD when operating the serial interface in I2C mode. -
5
6
7
GND
VDD
D+/AIN1
Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
D+. Positive Connection to External Temperature Sensor.
AIN1. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD.
D–. Negative Connection to External Temperature Sensor.
AIN2. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD.
8
9
D–/AIN2
LDAC/AIN3 LDAC. Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. A
falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum
pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows simul-
taneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin. Default is with
the LDAC pin controlling the loading of the DAC registers.
AIN3. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD.
10
11
INT/INT
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
temperature,VDD, or AIN limits are exceeded. The default is active low. Open-drain output—needs a pull-up resistor.
DOUT/ADD SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling
edge of SCLK. Open-drain output—needs a pull-up resistor.
ADD. I2C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000; leaving it floating
gives the address 1001 010; and setting it high gives the address 1001 011. The I2C address set up by the ADD pin is
not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid
communication, the serial bus address is latched in. Any subsequent changes on this pin will have no effect on the I2C
serial bus address.
12
13
SDA/DIN
SCL/SCLK
SDA. I2C Serial Data Input/Output. I2C serial data to be loaded into the part’s registers and read from these registers is
provided on this pin. Open-drain configuration—needs a pull-up resistor.
DIN. SPI Serial Data Input. Serial data to be loaded into the part’s registers is provided on this pin. Data is clocked into
a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor.
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of
the ADT7516/ADT7517/ADT7519 and also to clock data into any register that can be written to. Open-drain
configuration—needs a pull-up resistor.
14
15
16
AIN4
VOUT-D
VOUT-C
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD.
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Rev. A | Page 10 of 44
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