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ADT7518ARQ-REEL PDF预览

ADT7518ARQ-REEL

更新时间: 2024-02-11 08:04:42
品牌 Logo 应用领域
亚德诺 - ADI 传感器换能器温度传感器输出元件
页数 文件大小 规格书
40页 1349K
描述
SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DAC

ADT7518ARQ-REEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:LEAD FREE, MO-137-AB, QSOP-16
Reach Compliance Code:unknown风险等级:5.28
最大精度(摄氏度):5 Cel主体宽度:3.91 mm
主体高度:1.55 mm主体长度或直径:4.9 mm
外壳:PLASTICJESD-609代码:e3
安装特点:SURFACE MOUNT位数:10
最大工作电流:0.001 mA最高工作温度:120 °C
最低工作温度:-40 °C输出接口类型:4-WIRE INTERFACE
封装形状/形式:RECTANGULAR传感器/换能器类型:TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL
最大供电电压:5.5 V最小供电电压:2.7 V
表面贴装:YES端子面层:MATTE TIN
端接类型:SOLDERBase Number Matches:1

ADT7518ARQ-REEL 数据手册

 浏览型号ADT7518ARQ-REEL的Datasheet PDF文件第2页浏览型号ADT7518ARQ-REEL的Datasheet PDF文件第3页浏览型号ADT7518ARQ-REEL的Datasheet PDF文件第4页浏览型号ADT7518ARQ-REEL的Datasheet PDF文件第6页浏览型号ADT7518ARQ-REEL的Datasheet PDF文件第7页浏览型号ADT7518ARQ-REEL的Datasheet PDF文件第8页 
ADT7518  
Parameter1  
Min  
Typ  
Max  
Unit  
Conditions/Comments  
DIGITAL OUTPUT  
Digital High Voltage, VOH  
Output Low Voltage, VOL  
Output High Current, IOH  
Output Capacitance, COUT  
INT/INT Output Saturation Voltage  
2.4  
V
V
mA  
pF  
V
ISOURCE = ISINK = 200 µA.  
IOL = 3 mA.  
VOH = 5 V.  
0.4  
1
50  
0.8  
I
OUT = 4 mA.  
I2C TIMING CHARACTERISTICS 8, 9  
Serial Clock Period, t1  
Data In Setup Time to SCL High, t2  
Data Out Stable after SCL Low, t3  
SDA Low Setup Time to SCL  
Low (Start Condition), t4  
2.5  
50  
0
µs  
ns  
ns  
ns  
Fast Mode I2C. See Figure 2.  
See Figure 2.  
See Figure 2.  
50  
SDA High Hold Time after SCL  
High (Stop Condition), t5  
50  
ns  
ns  
See Figure 2.  
See Figure 2.  
SDA and SCL Fall Time, t6  
SPI TIMING CHARACTERISTICS4, 10  
CS to SCLK Setup Time, t1  
SCLK High Pulse Width, t2  
SCLK Low Pulse Width, t3  
90  
35  
0
ns  
ns  
ns  
ns  
See Figure 3.  
See Figure 3.  
See Figure 3.  
50  
50  
Data Access Time after SCLK  
11  
Falling Edge, t4  
Data Setup Time Prior to SCLK  
Rising Edge, t5  
Data Hold Time after SCLK Rising  
Edge, t6  
20  
0
ns  
ns  
See Figure 3.  
See Figure 3.  
CS to SCLK Hold Time, t7  
0
µs  
ns  
See Figure 3.  
See Figure 3.  
CS to DOUT High Impedance, t8  
40  
POWER REQUIREMENTS  
VDD  
VDD Settling Time  
IDD (Normal Mode) 12  
2.7  
5.5  
50  
3
V
ms  
mA  
mA  
µA  
µA  
mW  
µW  
VDD settles to within 10% of its final voltage level.  
VDD = 3.3 V, VIH = VDD, and VIL = GND.  
VDD = 5 V, VIH = VDD, and VIL = GND.  
VDD = 3.3 V, VIH = VDD, and VIL = GND.  
VDD = 5 V, VIH = VDD, and VIL = GND.  
VDD = 3.3 V. Normal mode.  
2.2  
3
IDD (Power-Down Mode)  
Power Dissipation  
10  
10  
10  
33  
VDD = 3.3 V. Shutdown mode.  
1 See the Terminology section.  
2 DC specifications are tested with the outputs unloaded.  
3 Linearity is tested using a reduced code range: ADT7518 (Code 8 to 255).  
4 Guaranteed by design and characterization, not production tested.  
5 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.  
6 The temperature accuracy specifications are valid when the internal reference is not being used by the on-chip DAC. For new designs, the ADT7519 is recommended  
as it does not have this limitation.  
7 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (VREF = VDD), the offset  
plus gain error must be positive.  
8 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate  
but has a negative effect on the EMC behavior of the part.  
9 Guaranteed by design, not production tested.  
10 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.  
11 Measured with the load circuit shown in Figure 4.  
12 The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.  
Rev. A | Page 5 of 40  
 
 
 
 

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