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ADSP-BF525 PDF预览

ADSP-BF525

更新时间: 2024-11-20 08:20:15
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
80页 4702K
描述
Blackfin Embedded Processor

ADSP-BF525 数据手册

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Blackfin® Embedded Processor  
Preliminary Technical Data  
ADSP-BF522/523/524/525/526/527  
FEATURES  
PERIPHERALS  
Up to 600 MHz high-performance Blackfin processor  
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,  
40-bit shifter  
USB 2.0 high speed on-the-go (OTG) with Integrated PHY  
IEEE 802.3-compliant 10/100 Ethernet MAC  
Parallel peripheral interface (PPI), supporting ITU-R 656  
video data formats  
RISC-like register and instruction model for ease of  
programming and compiler-friendly support  
Advanced debug, trace, and performance monitoring  
Accepts a wide range of supply voltages for internal and I/O  
operations. See Operating Conditions for  
ADSP-BF523/525/527 on Page 29 and Operating Condi-  
tions for ADSP-BF522/524/526 on Page 27  
Programmable on-chip voltage regulator  
(ADSP-BF523/525/527 processors only)  
Host DMA port (HOSTDP)  
Two dual-channel, full-duplex synchronous serial ports  
(SPORTs), supporting eight stereo I2S channels  
12 peripheral DMAs, 2 mastered by the Ethernet MAC  
Two memory-to-memory DMAs with external request lines  
Event handler with 54 interrupt inputs  
Serial peripheral interface (SPI) compatible port  
Two UARTs with IrDA® support  
289-ball (12 mm x 12 mm) and 208-ball (17 mm x 17 mm)  
CSP_BGA packages  
Two-wire interface (TWI) controller  
Eight 32-bit timers/counters with PWM support  
32-bit up/down counter with rotary support  
Real-time clock (RTC) and watchdog timer  
32-bit core timer  
48 general-purpose I/Os (GPIOs), with programmable  
hysteresis  
NAND flash controller (NFC)  
Debug/JTAG interface  
On-chip PLL capable of 0.5
؋
to 64
؋
 frequency multiplication  
MEMORY  
132K bytes of on-chip memory:  
(See Table 1 on Page 3 for L1 and L3 memory size details)  
External memory controller with glueless support for SDRAM  
and asynchronous 8-bit and 16-bit memories  
Flexible booting options from external flash, SPI, and TWI  
memory or from host devices including SPI, TWI, and UART  
Code Security with LockboxTM Secure Technology  
One-Time-Programmable (OTP) Memory  
Memory management unit providing memory protection  
WATCHDOG TIMER  
OTP MEMORY  
RTC  
VOLTAGE REGULATOR*  
JTAG TEST AND EMULATION  
PERIPHERAL  
COUNTER  
SPORT0  
SPORT1  
UART1  
UART0  
NFC  
ACCESS BUS  
INTERRUPT  
CONTROLLER  
GPIO  
PORT F  
B
L1 INSTRUCTION  
MEMORY  
L1 DATA  
GPIO  
PORT G  
DMA  
MEMORY  
PPI  
CONTROLLER  
DMA  
ACCESS  
BUS  
EAB  
16  
SPI  
DCB  
USB  
TIMER7-1  
TIMER0  
GPIO  
PORT H  
DEB  
BOOT  
ROM  
EXTERNAL PORT  
FLASH, SDRAM CONTROL  
EMAC  
HOST DMA  
TWI  
PORT J  
*REGULATOR AVAILABLE ON ADSP-BF523/525/527 PROCESSORS ONLY  
Figure 1. Processor Block Diagram  
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.  
Rev. PrG  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2009 Analog Devices, Inc. All rights reserved.  

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