Datasheet > ADSP-2185LBST-133

ADSP-2185LBST-133

更新时间： 2024-01-16 05:38:58

品牌	Logo	应用领域
亚德诺 - ADI		电脑
页数	文件大小	规格书
31页	224K
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DSP Microcomputer

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ADSP-2185LBST-133 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LFQFP, QFP100,.63SQ,20
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.A.2	HTS代码：	8542.31.00.01
风险等级：	5.36	地址总线宽度：	14
桶式移位器：	YES	边界扫描：	NO
外部数据总线宽度：	24	格式：	FLOATING POINT
集成缓存：	NO	内部总线架构：	MULTIPLE
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e0
长度：	14 mm	低功率模式：	YES
湿度敏感等级：	3	外部中断装置数量：	6
端子数量：	100	片上数据RAM宽度：	16
片上程序ROM宽度：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
认证状态：	Not Qualified	RAM（字数）：	8192
ROM可编程性：	FLASH	座面最大高度：	1.6 mm
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

ADSP-2185LBST-133 数据手册

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ADSP-2185L

Reset

FULL MEMORY MODE

The RESET signal initiates a master reset of the ADSP-2185L.

The RESET signal must be asserted during the power-up se-

quence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock

to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

ADSP-2185L

1/2x CLOCK

13-0

CLKIN

ADDR13-0

XTAL

CRYSTAL

A0-A21

23-16

FL0-2

BYTE

MEMORY

15-8

PF3

DATA

DATA23-0

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

BMS

10-0

IRQL1/PF6

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis ap-

plied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum

of 2000 CLKIN cycles ensures that the PLL has locked, but

does not include the crystal oscillator start-up time. During this

power-up sequence the RESET signal should be held low. On

any subsequent resets, the RESET signal must meet the mini-

ADDR

DATA

PF2 [MODE C]

PF1 [MODE B]

PF0 [MODE A]

23-8

I/O SPACE

(PERIPHERALS)

2048 LOCATIONS

IOMS

13-0

ADDR

DATA

SPORT1

SCLK1

RFS1 OR IRQ0

OVERLAY

MEMORY

23-0

SERIAL

DEVICE

TFS1 OR IRQ1

DT1 OR FL0

DR1 OR FL1

TWO 8K

PMS

DMS

CMS

PM SEGMENTS

TWO 8K

DM SEGMENTS

SPORT0

SCLK0

RFS0

TFS0

DT0

DR0

mum pulsewidth specification, t_RSP

SERIAL

DEVICE

BGH

The RESET input contains some hysteresis; however, if an

RC circuit is used to generate the RESET signal, an external

Schmidt trigger is recommended.

PWD

PWDACK

HOST MEMORY MODE

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MSTAT

request and the chip is configured for booting, the boot-loading

sequence is performed. The first instruction is fetched from

on-chip program memory location 0x0000 once boot loading

completes.

ADSP-2185L

CLKIN

1/2x CLOCK

CRYSTAL

XTAL

FL0-2

PF3

DATA23-8

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

BMS

IRQL1/PF6

PF2 [MODE C]

PF1 [MODE B]

PF0 [MODE A]

MODES OF OPERATION

Table II summarizes the ADSP-2185L memory modes.

IOMS

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

Setting Memory Mode

SERIAL

DEVICE

Memory Mode selection for the ADSP-2185L is made during

chip reset through the use of the Mode C pin. This pin is multi-

plexed with the DSP’s PF2 pin, so care must be taken in how

the mode selection is made. The two methods for selecting the

value of Mode C are active and passive.

DT1 OR FO

DR1 OR FI

PMS

DMS

CMS

SPORT0

SCLK0

RFS0

TFS0

DT0

SERIAL

DEVICE

BGH

DR0

IDMA PORT

IRD/D6

IWR/D7

IS/D4

IAL/D5

IACK/D3

IAD15-0

Passive configuration involves the use a pull-up or pull-down

resistor connected to the Mode C pin. To minimize power con-

sumption, or if the PF2 pin is to be used as an output in the

DSP application, a weak pull-up or pull-down, on the order of

100 kΩ, can be used. This value should be sufficient to pull the

pin to the desired level and still allow the pin to operate as

a programmable flag output without undue strain on the

processor’s output driver. For minimum power consumption

during power-down, reconfigure PF2 to be an input, as the

pull-up or pull-down will hold the pin in a known state, and will

not switch.

PWD

PWDACK

SYSTEM

INTERFACE

␮CONTROLLER

Figure 2. ADSP-2185L Basic System Configuration

XTAL

CLKIN

CLKOUT

DSP

Active configuration involves the use of a three-statable exter-

nal driver connected to the Mode C pin. A driver’s output en-

able should be connected to the DSP’s RESET signal such that

it only drives the PF2 pin when RESET is active (low). When

RESET is deasserted, the driver should three-state, thus allow-

ing full use of the PF2 pin as either an input or output. To

minimize power consumption during power-down, configure

the programmable flag as an output when connected to a three-

stated buffer. This ensures that the pin will be held at a con-

stant level and not oscillate should the three-state driver’s level

hover around the logic switching point.

Figure 3. External Crystal Connections

REV. A

–7–

1...4 5 678 9 10...31

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