Datasheet > ADSP-2185LBST-133

ADSP-2185LBST-133

更新时间： 2024-02-04 14:52:03

品牌	Logo	应用领域
亚德诺 - ADI		电脑
页数	文件大小	规格书
31页	224K
描述
DSP Microcomputer

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技术参数
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替代型号

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ADSP-2185LBST-133 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LFQFP, QFP100,.63SQ,20
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.A.2	HTS代码：	8542.31.00.01
风险等级：	5.36	地址总线宽度：	14
桶式移位器：	YES	边界扫描：	NO
外部数据总线宽度：	24	格式：	FLOATING POINT
集成缓存：	NO	内部总线架构：	MULTIPLE
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e0
长度：	14 mm	低功率模式：	YES
湿度敏感等级：	3	外部中断装置数量：	6
端子数量：	100	片上数据RAM宽度：	16
片上程序ROM宽度：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
认证状态：	Not Qualified	RAM（字数）：	8192
ROM可编程性：	FLASH	座面最大高度：	1.6 mm
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

ADSP-2185LBST-133 数据手册

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ADSP-2185L

DATA MEMORY

Composite Memory Select (CMS)

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-mapped

control registers. The ADSP-2185L has 16K words on Data

Memory RAM on chip, consisting of 16,352 user-accessible lo-

cations and 32 memory-mapped registers. Support also exists

for up to two 8K external memory overlay spaces through the

external data bus. All internal accesses complete in one cycle.

Accesses to external memory are timed using the wait states

specified by the DWAIT register.

The ADSP-2185L has a programmable memory select signal

that is useful for generating memory select signals for memories

mapped to more than one space. The CMS signal is generated

to have the same timing as each of the individual memory select

signals (PMS, DMS, BMS, IOMS) but can combine their

functionality.

Each bit in the CMSSEL register, when set, causes the CMS

signal to be asserted when the selected memory select is as-

serted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip select

of the memory; use either DMS or PMS as the additional

address bit.

DATA MEMORY

ADDRESS

3FFF

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

ALWAYS

ACCESSIBLE

AT ADDRESS

0x3FE0

0x3FDF

0x2000 – 0x3FFF

INTERNAL

8160

WORDS

INTERNAL

MEMORY

0x0000–

0x1FFF

0x2000

The CMS pin functions like the other memory select signals,

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at re-

set, except the BMS bit.

ACCESSIBLE WHEN

DMOVLAY = 0

0x1FFF

0x0000–

0x1FFF

8K INTERNAL

DMOVLAY = 0

EXTERNAL 8K

DMOVLAY = 1, 2

ACCESSIBLE WHEN

DMOVLAY = 1

0x0000–

0x1FFF

EXTERNAL

MEMORY

0x0000

ACCESSIBLE WHEN

DMOVLAY = 2

Boot Memory Select (BMS) Disable

Figure 5. Data Memory Map

The ADSP-2185L also lets you boot the processor from one ex-

ternal memory space while using a different external memory

space for BDMA transfers during normal operation. You can

use the CMS to select the first external memory space for

BDMA transfers and BMS to select the second external memory

space for booting. The BMS signal can be disabled by setting

Bit 3 of the System Control Register to 1. The System Control

Data Memory (Host Mode) allows access to all internal memory.

External overlay access is limited by a single external address

line (A0). The DMOVLAY bits are defined in Table IV.

Table IV. DMOVLAY Bits

DMOVLAY Memory A13

A12:0

Internal

Not Applicable Not Applicable

SYSTEM CONTROL REGISTER

15 14 13 12 11 10

External

Overlay 1

13 LSBs of Address

Between 0x2000

and 0x3FFF

DM (0

3FFF)

PWAIT

PROGRAM MEMORY

WAIT STATES

SPORT0 ENABLE

1 = ENABLED, 0 = DISABLED

SPORT1 ENABLE

1 = ENABLED, 0 = DISABLED

External

Overlay 2

13 LSBs of Address

Between 0x2000

and 0x3FFF

BMS ENABLE

0 = ENABLED, 1 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = FI, FO, IRQ0, IRQ1, SCLK

Figure 6. System Control Register

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The BDMA Control Register is

shown in Figure 7. The byte memory space consists of 256 pages,

each of which is 16K × 8.

I/O Space (Full Memory Mode)

The ADSP-2185L supports an additional external memory

space called I/O space. This space is designed to support simple

connections to peripherals (such as data converters and external

registers) or to bus interface ASIC data registers. I/O space sup-

ports 2048 locations of 16-bit wide data. The lower eleven bits

of the external address bus are used; the upper three bits are un-

defined. Two instructions were added to the core ADSP-2100

Family instruction set to read from and write to I/O memory

space. The I/O space also has four dedicated 3-bit wait state

registers, IOWAIT0-3, that specify up to seven wait states to be

automatically generated for each of four regions. The wait states

act on address ranges as shown in Table V.

BDMA CONTROL

15 14 13 12 11 10

DM (0

3FE3)

BTYPE

BDIR

BMPAGE

0 = LOAD FROM BM

1 = STORE TO BM

Table V. Wait States

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

Address Range

Wait State Register

Figure 7. BDMA Control Register

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0

IOWAIT1

IOWAIT2

IOWAIT3

The byte memory space on the ADSP-2185L supports read and

write operations as well as four different data formats. The byte

memory uses data bits 15:8 for data. The byte memory uses

data bits 23:16 and address bits 13:0 to create a 22-bit address.

This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by

the BMWAIT register.

REV. A

–9–

1...6 7 8910 11 12...31

中文翻译

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ADSP-2185LBST-133 替代型号

型号	品牌	替代类型	描述	数据表
ADSP-2185LBSTZ-133	ADI	完全替代	IC 24-BIT, 26.3 MHz, OTHER DSP, PQFP100, ROHS COMPLIANT, MS-026BED, LQFP-100, Digital Sign
ADSP-2185LKST-133	ADI	完全替代	DSP Microcomputer
ADSP-2185LKST-160	ADI	类似代替	DSP Microcomputer

与ADSP-2185LBST-133相关器件

型号	品牌	获取价格	描述	数据表
ADSP-2185LBST-160	ADI	获取价格	DSP Microcomputer
ADSP-2185LBST-210	ADI	获取价格	DSP Microcomputer
ADSP-2185LBSTZ-133	ADI	获取价格	IC 24-BIT, 26.3 MHz, OTHER DSP, PQFP100, ROHS COMPLIANT, MS-026BED, LQFP-100, Digital Sign
ADSP-2185LBSTZ-1332	ADI	获取价格	DSP Microcomputer
ADSP-2185LBSTZ-160	ADI	获取价格	IC 24-BIT, 26.3 MHz, OTHER DSP, PQFP100, ROHS COMPLIANT, MS-026BED, LQFP-100, Digital Sign
ADSP-2185LBSTZ-1602	ADI	获取价格	DSP Microcomputer
ADSP-2185LBSTZ-210	ADI	获取价格	16-bit, 52 MIPS, 3.3v, 2 serial ports, host port, 80 KB RAM
ADSP-2185LBSTZ-2102	ADI	获取价格	DSP Microcomputer
ADSP-2185LKST-115	ADI	获取价格	DSP Microcomputer
ADSP-2185LKST-133	ADI	获取价格	DSP Microcomputer

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