Datasheet > ADSP-21371

ADSP-21371

更新时间： 2024-02-02 04:42:48

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
48页	1996K
描述
SHARC Processor

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技术参数
数据手册

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ADSP-21371 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LEAD FREE, MQFP-208	针数：	208
Reach Compliance Code：	unknown	ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01	风险等级：	5.84
地址总线宽度：	24	桶式移位器：	YES
边界扫描：	YES	最大时钟频率：	133 MHz
外部数据总线宽度：	32	格式：	FLOATING POINT
内部总线架构：	MULTIPLE	JESD-30 代码：	S-PQFP-G208
JESD-609代码：	e3	长度：	28 mm
低功率模式：	YES	端子数量：	208
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	4.1 mm
最大供电电压：	1.26 V	最小供电电压：	1.14 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	28 mm
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER

ADSP-21371 数据手册

ADSP-21371

Preliminary Technical Data

Up to 16 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port, configurable as eight channels of serial data

or seven channels of serial data and up to a 20-bit wide

parallel data channel

Signal routing unit provides configurable and flexible con-

nections between all DAI/DPI components

2 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line /MS pin

S/PDIF compatible digital audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I²S or right-justified serial data input with

16, 18, 20 or 24-bit word widths (transmitter)

Pulse width modulation provides:

KEY FEATURES – PROCESSOR CORE

At 266 MHz (3.75 ns) core instruction rate, the ADSP-21371

performs 1.596 GFLOPs/533 MMACs

1M bit on-chip, SRAM for simultaneous access by the core

processor and DMA

4M bit on-chip, mask-programmable, ROM

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single instruction multiple data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Parallelism in buses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of a multiply

operation, an ALU operation, a dual memory read or

write, and an instruction fetch

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms

1 Muxed Flag/IRQ /MS pin

ROM Based Security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Transfers between memory and core at a sustained 4.25G

byte/sec bandwidth at 266 MHz core instruction rate

INPUT/OUTPUT FEATURES

Dual voltage: 3.3 V I/O, 1.2 V core

DMA controller supports:

Available in 208-lead MQFP Package (see Ordering Guide on

Page 47)

32 DMA channels for transfers between ADSP-21371 inter-

nal memory and a variety of peripherals

32-bit DMA transfers at peripheral clock speed, in parallel

with full-speed processor execution

32-Bit wide external port provides glueless connection to

both synchronous (SDRAM) and asynchronous memory

devices

Programmable wait state options: 2 to 31 SDCLK cycles

Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset based reads

SDRAM accesses at 133 MHz and asynchronous accesses at

44.4 MHz

4 memory select lines allows multiple external memory

devices

Digital audio interface (DAI) includes eight serial ports, four

precision clock generators, an input data port, an S/PDIF

transceiver, and a signal routing unit

Digital peripheral interface (DPI) includes, two timers, one

UART, and two SPI ports, and a two wire interface port

Outputs of PCG's C and D can be driven on to DPI pins

Eight dual data line serial ports that operate at up to 33M

bits/s on each data line — each has a clock, frame sync and

two data lines that can be configured as either a receiver or

transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Rev. PrA

Page 2 of 48

June 2006

123 4 5 6 7...48

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与ADSP-21371相关器件

型号	品牌	描述	获取价格	数据表
ADSP-21371_07	ADI	SHARC㈢ Processor	获取价格
ADSP-21371_09	ADI	SHARC Processor optimized for high performance audio processing	获取价格
ADSP-21371BSWZ-2B	ADI	High-Performance 32-bit Floating-Point SHARC Processor for Automotive Audio	获取价格
ADSP-21371BSWZ-2B2	ADI	SHARC Processor optimized for high performance audio processing	获取价格
ADSP-21371KSWZ-2A	ADI	32-BIT, 16.67MHz, OTHER DSP, PQFP208, ROHS COMPLIANT, MS-026BJB-HD, LQFP-208	获取价格
ADSP-21371KSWZ-2A2	ADI	SHARC Processor optimized for high performance audio processing	获取价格

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