5秒后页面跳转
ADSP-21262SKBC-200X PDF预览

ADSP-21262SKBC-200X

更新时间: 2024-01-03 22:26:24
品牌 Logo 应用领域
亚德诺 - ADI 时钟外围集成电路
页数 文件大小 规格书
44页 1381K
描述
IC 16-BIT, 66.66 MHz, OTHER DSP, PBGA136, MO-205AE, BGA-136, Digital Signal Processor

ADSP-21262SKBC-200X 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:MO-205AE, BGA-136
针数:136Reach Compliance Code:not_compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.17地址总线宽度:16
桶式移位器:YES位大小:32
边界扫描:YES最大时钟频率:66.66 MHz
外部数据总线宽度:16格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B136
JESD-609代码:e0长度:12 mm
低功率模式:NO端子数量:136
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA136,14X14,32封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.2,3.3 V认证状态:Not Qualified
RAM(字数):65536座面最大高度:1.7 mm
子类别:Digital Signal Processors最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:12 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

ADSP-21262SKBC-200X 数据手册

 浏览型号ADSP-21262SKBC-200X的Datasheet PDF文件第5页浏览型号ADSP-21262SKBC-200X的Datasheet PDF文件第6页浏览型号ADSP-21262SKBC-200X的Datasheet PDF文件第7页浏览型号ADSP-21262SKBC-200X的Datasheet PDF文件第9页浏览型号ADSP-21262SKBC-200X的Datasheet PDF文件第10页浏览型号ADSP-21262SKBC-200X的Datasheet PDF文件第11页 
PRELIMINARY TECHNICAL DATA  
For current information contact Analog Devices at 800/262-5643  
August 2003  
ADSP-21262  
Power Supplies  
real-time characteristics of the program. Essentially, the  
The ADSP-21262 has separate power supply connections for the  
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS  
power supplies. The internal and analog supplies must meet the  
1.2V requirement. The external supply must meet the 3.3V  
requirement. All external supply pins must be connected to the  
same power supply.  
developer can identify bottlenecks in software quickly and effi-  
ciently. By using the profiler, the programmer can focus on those  
areasintheprogramthatimpactperformanceandtakecorrective  
action.  
)
Debugging both C/C++ and assembly programs with the  
VisualDSP++ debugger, programmers can:  
Note that the analog supply (AVDD) powers the ADSP-21262’s  
clock generator PLL. To produce a stable clock, you should  
provide an external circuit to filter the power input to the AVDD  
pin. Place the filter as close as possible to the pin. For an example  
circuit, see Figure 3. To prevent noise coupling, use a wide trace  
for the analog ground (AVSS) signal and install a decoupling  
capacitor as close as possible to the pin. Note that the AVSS and  
AVDD pins specified in Figure 3 are inputs to the DSP and not the  
analog ground plane on the board.  
View mixed C/C++ and assembly code (interleaved  
source and object information)  
Insert breakpoints  
Set conditional breakpoints on registers, memory,  
and stacks  
Trace instruction execution  
Perform linear or statistical profiling of program  
execution  
Fill, dump, and graphically plot the contents of memory  
Perform source level debugging  
10  
V
A
VDD  
DDINT  
Create custom debugger windows  
0.1F  
0.01F  
The VisualDSP++ IDDE lets programmers define and manage  
DSP software development. Its dialog boxes and property pages  
let programmers configure and manage all of the ADSP-21xxx  
development tools, including the color syntax highlighting in the  
VisualDSP++ editor. This capability permits programmers to:  
A
VSS  
Figure 3. Analog Power (AVDD) Filter Circuit  
Control how the development tools process inputs and  
generate outputs  
Development Tools  
The ADSP-21262 is supported with a complete set of  
Maintain a one-to-one correspondence with the tool’s  
command line switches  
CROSSCORE™ software and hardware development tools,  
including Analog Devices emulators and VisualDSP++™ devel-  
opment environment. The same emulator hardware that  
supports other ADSP-21xxx processors also fully emulates the  
ADSP-21262.  
The VisualDSP++ Kernel (VDK) incorporates scheduling and  
resourcemanagementtailoredspecificallytoaddressthememory  
and timing constraints of DSP programming. These capabilities  
enableengineerstodevelopcodemoreeffectively,eliminatingthe  
need to start from the very beginning, when developing new  
application code. The VDK features include Threads, Critical  
andUnscheduledregions,Semaphores,Events,andDeviceflags.  
The VDK also supports Priority-based, Preemptive, Coopera-  
tive, and Time-Sliced scheduling approaches. In addition, the  
VDK was designed to be scalable. If the application does not use  
a specific feature, the support code for that feature is excluded  
from the target system.  
The VisualDSP++ project management environment lets pro-  
grammers develop and debug an application. This environment  
includes an easy to use assembler (which is based on an algebraic  
syntax), an archiver (librarian/library builder), a linker, a loader,  
a cycle-accurate instruction-level simulator, a C/C++ compiler,  
and a C/C++ runtime library that includes DSP and mathemat-  
ical functions. A key point for these tools is C/C++ code  
efficiency. The compiler has been developed for efficient transla-  
tion of C/C++ code to DSP assembly. The DSP has architectural  
features that improve the efficiency of compiled C/C++ code.  
Because the VDK is a library, a developer can decide whether to  
use it or not. TheVDKis integrated intothe VisualDSP++ devel-  
opment environment, but can also be used via standard  
command line tools. When the VDK is used, the development  
environment assists the developer with many error-prone tasks  
and assists in managing system resources, automating the gener-  
ation of various VDK based objects, and visualizing the system  
state, when debugging an application that uses the VDK.  
TheVisualDSP++debuggerhasanumberofimportantfeatures.  
Data visualization is enhanced by a plotting package that offers  
a significant level of flexibility. This graphical representation of  
user data enables the programmer to quickly determine the per-  
formance of an algorithm. As algorithms grow in complexity, this  
capability can have increasing significance on the designer’s  
development schedule, increasing productivity. Statistical  
profiling enables the programmer to non intrusively poll the  
processor as it is running the program. This feature, unique to  
VisualDSP++, enables the software developer to passively gather  
important code execution metrics without interrupting the  
VisualDSP++ Component Software Engineering (VCSE) is  
Analog Devices technology for creating, using, and reusing  
software components (independent modules of substantial func-  
tionality) to quickly and reliably assemble software applications.  
Download components from the Web and drop them into the  
This information applies to a product under development. Its characteristics and specifications are subject to change without  
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.  
PrB  
8

与ADSP-21262SKBC-200X相关器件

型号 品牌 获取价格 描述 数据表
ADSP-21262SKBCZ200 ADI

获取价格

SHARC Processor
ADSP-21262SKSTZ200 ADI

获取价格

SHARC Processor
ADSP-21262SKSTZX ADI

获取价格

IC 16-BIT, 66.66 MHz, OTHER DSP, PQFP144, MS-026BFB, LQFP-144, Digital Signal Processor
ADSP-21266 ADI

获取价格

SHARC Embedded Processor
ADSP-21266_07 ADI

获取价格

Embedded Processor
ADSP-21266SKBC-200X ADI

获取价格

IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC
ADSP-21266SKBC-2B ADI

获取价格

SHARC Embedded Processor
ADSP-21266SKBCZ-2B ADI

获取价格

SHARC Embedded Processor
ADSP-21266SKBCZ-2C ADI

获取价格

SHARC Embedded Processor
ADSP-21266SKBCZ-2D ADI

获取价格

SHARC Embedded Processor