ADSP-21261
TABLE OF CONTENTS
General Description ................................................. 4
ADSP-21261 Family Core Architecture ...................... 4
SIMD Computational Engine ............................... 4
Independent, Parallel Computation Units ................ 4
Data Register File ............................................... 5
Reset ............................................................. 20
Interrupts ....................................................... 20
Core Timer ..................................................... 20
Timer PWM_OUT Cycle Timing ......................... 21
Timer WDTH_CAP Timing ............................... 21
DAI Pin-to-Pin Direct Routing ............................ 22
Precision Clock Generator (Direct Pin Routing) ...... 23
Flags ............................................................. 24
Memory Read—Parallel Port ............................... 25
Memory Write—Parallel Port ............................. 27
Serial Ports ..................................................... 29
Input Data Port (IDP) ....................................... 32
Parallel Data Acquisition Port (PDAP) .................. 33
SPI Protocol—Master ........................................ 34
SPI Protocol—Slave .......................................... 34
JTAG Test Access Port and Emulation .................. 36
Output Drive Currents ......................................... 37
Test Conditions .................................................. 37
Capacitive Loading .............................................. 37
Environmental Conditions .................................... 38
Thermal Characteristics ........................................ 38
136-Ball BGA Pin Configurations ............................... 39
144-Lead LQFP Pin Configurations ............................ 42
Package Dimensions ............................................... 43
Surface Mount Design .......................................... 44
Ordering Guide ..................................................... 44
Single-Cycle Fetch of Instruction and
Four Operands ............................................... 5
Instruction Cache .............................................. 5
Data Address Generators with Zero-Overhead
Hardware Circular Buffer Support ...................... 5
Flexible Instruction Set ....................................... 6
ADSP-21261 Memory and I/O Interface Features ......... 6
Dual-Ported On-Chip Memory ............................. 6
DMA Controller ................................................ 6
Digital Applications Interface (DAI) ....................... 6
Serial Ports ....................................................... 6
Serial Peripheral (Compatible) Interface .................. 7
Parallel Port ..................................................... 7
Timers ............................................................ 8
Program Booting ............................................... 8
Phase-Locked Loop ............................................ 8
Power Supplies .................................................. 8
Target Board JTAG Emulator Connector .................... 8
Development Tools ............................................... 8
Evaluation Kit ..................................................... 10
Designing an Emulator-Compatible
DSP Board (Target) ........................................... 10
Additional Information ......................................... 10
Pin Function Descriptions ........................................ 11
Address Data Pins as Flags ..................................... 14
Boot Modes ........................................................ 14
Core Instruction Rate to CLKIN Ratio Modes ............. 14
Address Data Modes ............................................. 14
ADSP-21261 Specifications ....................................... 15
Recommended Operating Conditions ....................... 15
Electrical Characteristics ........................................ 15
Absolute Maximum Ratings ................................... 16
ESD Sensitivity .................................................... 16
Timing Specifications ........................................... 17
Power-Up Sequencing ....................................... 18
Clock Input ..................................................... 19
Clock Signals ................................................... 19
REVISION HISTORY
3/06—Rev. 0: Initial Release
Rev. 0
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Page 3 of 44 | March 2006
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