ADSP-21xx
T he ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. T hese devices offer different
amounts of on-chip memory for program and data storage.
T able II shows the features available in the ADSP-216x series of
custom ROM-coded processors.
ARCH ITECTURE O VERVIEW
Figure 1 shows a block diagram of the ADSP-21xx architecture.
T he processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
T he computational units process 16-bit data directly and have
provisions to support multiprecision computations. T he ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. T he MAC performs
single-cycle multiply, multiply/add, and multiply/subtract
operations. T he shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control including multiword floating-point representations.
T he ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire applica-
tion program in on-chip ROM. T hese devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
D evelopm ent Tools
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
T he ADSP-21xx processors are supported by a complete set of
tools for system development. T he ADSP-2100 Family Devel-
opment Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-21xx
processors. T he ANSI C compiler generates ADSP-21xx
assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. T he ADSP-
21xx assembler produces object code modules which the linker
combines into an executable file. T he processor simulators
provide an interactive instruction-level simulation with a
reconfigurable, windowed user interface. A PROM splitter
utility generates PROM programmer compatible files.
EZ-ICE® in-circuit emulators allow debugging of ADSP-21xx
systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB® demonstration boards are complete DSP
systems that execute EPROM-based programs.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
T he sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-21xx executes looped code with zero
overhead—no explicit jump instructions are required to
maintain the loop.
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. T he circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
T he EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Efficient data transfer is achieved with the use of five internal
buses:
Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-T OOLS). T his data sheet can be requested
from any Analog Devices sales office or distributor.
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
Additional Infor m ation
T his data sheet provides a general overview of ADSP-21xx
processor functionality. For detailed design information on the
architecture and instruction set, refer to the ADSP-2100 Family
User’s Manual, available from Analog Devices.
T he two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
T he BMS, DMS, and PMS signals indicate which memory
space is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-21xx to fetch two operands in a single cycle, one
from program memory and one from data memory. T he
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
T he memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
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