ADSP-2104/ADSP-2109
INSTRUCTION
REGISTER
PROGRAM
MEMORY
DATA
MEMORY
BOOT
ADDRESS
GENERATOR
SRAM
or ROM
SRAM
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
TIMER
PROGRAM
SEQUENCER
24
16
PMA BUS
DMA BUS
14
PMA BUS
DMA BUS
EXTERNAL
ADDRESS
BUS
14
MUX
MUX
14
PMD BUS
DMD BUS
24
16
PMD BUS
24
EXTERNAL
DATA
BUS
BUS
EXCHANGE
DMD BUS
COMPANDING
CIRCUITRY
INPUT REGS
INPUT REGS
ALU
INPUT REGS
MAC
SHIFTER
TRANSMIT REG
RECEIVE REG
TRANSMIT REG
RECEIVE REG
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
16
SERIAL
PORT 0
SERIAL
PORT 1
R Bus
5
5
Figure 1. ADSP-2104/ADSP-2109 Block Diagram
ARCH ITECTURE O VERVIEW
circular buffers. T he circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
Figure 1 shows a block diagram of the ADSP-2104/ADSP-2109
architecture. T he processor contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. T he computational units process 16-bit data directly
and have provisions to support multiprecision computations.
T he ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. T he MAC
performs single-cycle multiply, multiply/add, and multiply/
subtract operations. T he shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations. The shifter can be used to efficiently implement
numeric format control including multiword floating-point
representations.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
T he two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
T he BMS, DMS, and PMS signals indicate which memory
space is using the external buses.
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
Program memory can store both instructions and data, permit-
ting the ADSP-2104/ADSP-2109 to fetch two operands in a
single cycle, one from program memory and one from data
memory. T he processor can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
T he sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2104/ADSP-2109 executes looped code
with zero overhead—no explicit jump instructions are required
to maintain the loop. Nested loops are also supported.
T he memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
One bus grant execution mode (GO Mode) allows the ADSP-
2104/ADSP-2109 to continue running from internal memory.
A second execution mode requires the processor to halt while
buses are granted.
REV. 0
–3–
5秒后页面跳转
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
一文带你了解压敏电阻器在直流电路中的过压保护作用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
