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ADSP-2101BGZ-100 PDF预览

ADSP-2101BGZ-100

更新时间： 2024-01-18 12:07:53
品牌 Logo 应用领域
亚德诺 - ADI 时钟外围集成电路装置
页数 文件大小 规格书
87页 738K
描述
IC 24-BIT, 25 MHz, OTHER DSP, PQCC68, PLASTIC, LCC-68, Digital Signal Processor

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ADSP-2101BGZ-100 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：68
Reach Compliance Code：compliantECCN代码：3A991.A.3
HTS代码：8542.31.00.01风险等级：5.58
地址总线宽度：14桶式移位器：YES
边界扫描：NO最大时钟频率：25 MHz
外部数据总线宽度：24格式：FIXED POINT
集成缓存：NO内部总线架构：MULTIPLE
JESD-30 代码：S-PQCC-J68JESD-609代码：e4
长度：24.18 mm低功率模式：YES
DMA 通道数量：外部中断装置数量：1
串行 I/O 数：2端子数量：68
计时器数量：1片上数据RAM宽度：16
片上程序ROM宽度：最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not QualifiedRAM（字数）：512
座面最大高度：4.45 mm最大压摆率：38 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Gold (Au)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：24.18 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

ADSP-2101BGZ-100 数据手册

 浏览型号ADSP-2101BGZ-100的Datasheet PDF文件第5页浏览型号ADSP-2101BGZ-100的Datasheet PDF文件第6页浏览型号ADSP-2101BGZ-100的Datasheet PDF文件第7页浏览型号ADSP-2101BGZ-100的Datasheet PDF文件第9页浏览型号ADSP-2101BGZ-100的Datasheet PDF文件第10页浏览型号ADSP-2101BGZ-100的Datasheet PDF文件第11页 
ADSP-21xx  
A clock output signal (CLKOUT ) is generated by the processor,  
synchronized to the processor’s internal cycles.  
T he power-up sequence is defined as the total time required for  
the crystal oscillator circuit to stabilize after a valid VDD is  
applied to the processor and for the internal phase-locked loop  
(PLL) to lock onto the specific crystal frequency. A minimum of  
2000 tCK cycles will ensure that the PLL has locked (this does  
not, however, include the crystal oscillator start-up time).  
During this power-up sequence the RESET signal should be  
held low. On any subsequent resets, the RESET signal must  
Reset  
The RESET signal initiates a complete reset of the ADSP-21xx.  
T he RESET signal must be asserted when the chip is powered  
up to assure proper initialization. If the RESET signal is applied  
during initial power-up, it must be held long enough to allow  
the processor’s internal clock to stabilize. If RESET is activated  
at any time after power-up and the input clock frequency does  
not change, the processor’s internal clock continues and does  
not require this stabilization time.  
meet the minimum pulse width specification, tRSP  
.
T o generate the RESET signal, use either an RC circuit with an  
external Schmidt trigger or a commercially available reset IC.  
(Do not use only an RC circuit.)  
Table IV. AD SP -21xx P in D efinitions  
P in  
Nam e(s)  
# of  
P ins  
Input /  
O utput  
Function  
Address  
Data1  
14  
24  
O
I/O  
Address outputs for program, data and boot memory.  
Data I/O pins for program and data memories. Input only for  
boot memory, with two MSBs used for boot memory addresses.  
Unused data lines may be left floating.  
Processor Reset Input  
External Interrupt Request # 2  
External Bus Request Input  
External Bus Grant Output  
External Program Memory Select  
External Data Memory Select  
Boot Memory Select  
External Memory Read Enable  
External Memory Write Enable  
Memory Map Select Input  
External Clock or Quartz Crystal Input  
Processor Clock Output  
Power Supply Pins  
RESET  
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
IRQ2  
BR2  
BG  
PMS  
DMS  
BMS  
RD  
WR  
MMAP  
CLKIN, XT AL  
CLKOUT  
VDD  
I
O
GND  
Ground Pins  
SPORT 03  
SPORT 1  
or Interrupts & Flags:  
IRQ0 (RFS1)  
IRQ1 (TFS1)  
FI (DR1)  
FO (DT1)  
FL2–0 (ADSP-2111 Only)  
5
5
I/O  
I/O  
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)  
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)  
1
1
1
1
3
I
I
I
O
O
External Interrupt Request # 0  
External Interrupt Request # 1  
Flag Input Pin  
Flag Output Pin  
General Purpose Flag Output Pins  
Host Interface Port  
(ADSP-2111 Only)  
HSEL  
HACK  
1
1
I
O
HIP Select Input  
HIP Acknowledge Output  
HSIZE  
BMODE  
HMD0  
HMD1  
HRD/HRW  
HWR/HDS  
HD15–0/HAD15-0  
HA2/ALE  
HA1–0/Unused  
1
1
1
1
1
1
16  
1
2
I
I
I
I
I
I
8/16-Bit Host Select (0 = 16-Bit, 1 = 8-Bit)  
Boot Mode Select (0 = Standard EPROM Booting, 1 = HIP Booting)  
Bus Strobe Select (0 = RD/WR, 1 = RW/DS)  
HIP Address/Data Mode Select (0 = Separate, 1 = Multiplexed)  
HIP Read Strobe or Read/Write Select  
HIP Write Strobe or Host Data Strobe Select  
HIP Data or HIP Data and Address  
I/O  
I
I
Host Address 2 Input or Address Latch Enable Input  
Host Address 1 and 0 Inputs  
NOT ES  
1Unused data bus lines may be left floating.  
2BR must be tied high (to VDD) if not used.  
3ADSP-2105 does not have SPORT 0. (SPORT 0 pins are No Connects on the ADSP-2105.)  
–8–  
REV. B  
1...567891011...87

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