ADSP-21xx
FLAGS
(ADSP-2111 Only)
INSTRUCTION
REGISTER
PROGRAM
MEMORY
DATA
MEMORY
3
BOOT
ADDRESS
GENERATOR
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
SRAM
or ROM
SRAM
TIMER
PROGRAM
SEQUENCER
24
16
PMA BUS
DMA BUS
14
PMA BUS
DMA BUS
14
EXTERNAL
ADDRESS
BUS
MUX
14
24
PMD BUS
PMD BUS
DMD BUS
24
EXTERNAL
DATA
BUS
EXCHANGE
MUX
BUS
16 DMD BUS
COMPANDING
CIRCUITRY
INPUT REGS
INPUT REGS
MAC
INPUT REGS
11
HOST
PORT
CONTROL
SHIFTER
ALU
EXTERNAL
HOST PORT
TRANSMIT REG
RECEIVE REG
TRANSMIT REG
RECEIVE REG
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
16
BUS
HOST
PORT
DATA
16
SERIAL
PORT 0
(Not on ADSP-2105)
SERIAL
PORT 1
R Bus
HOST INTERFACE PORT
(ADSP-2111 Only)
5
5
Figure 1. ADSP-21xx Block Diagram
Ser ial P or ts
One bus grant execution mode (GO Mode) allows the ADSP-
21xx to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
T he ADSP-21xx processors include two synchronous serial
ports (“SPORT s”) for serial communications and multiproces-
sor communication. All of the ADSP-21xx processors have two
serial ports (SPORT 0, SPORT 1) except for the ADSP-2105,
which has only SPORT 1.
Each ADSP-21xx processor can respond to several different
interrupts. T here can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer, serial ports, and, on the ADSP-2111,
the host interface port. T here is also a master RESET signal.
T he serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. T his allows, for
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Nam e
Function
SCLK
RFS
T FS
DR
Serial Clock (I/O)
T he data receive and transmit pins on SPORT 1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device. T he ADSP-2111 has three
additional flag outputs whose states are controlled through
software.
Receive Frame Synchronization (I/O)
T ransmit Frame Synchronization (I/O)
Serial Data Receive
DT
Serial Data T ransmit
T he ADSP-21xx serial ports offer the following capabilities:
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (T COUNT ) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(T SCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (T PERIOD).
Bidir ectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
REV. B
–5–