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ADS131M04IRUKR

更新时间: 2024-01-12 16:18:46
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
99页 2919K
描述
四通道、24 位、64kSPS、同步采样 Δ-Σ ADC | RUK | 20 | -40 to 125

ADS131M04IRUKR 技术参数

生命周期:Preview包装说明:QCCN,
Reach Compliance Code:compliant风险等级:5.76
转换器类型:ADC, DELTA-SIGMAJESD-30 代码:S-XQCC-N20
模拟输入通道数量:4位数:24
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出位码:2'S COMPLEMENT BINARY输出格式:SERIAL
封装主体材料:UNSPECIFIED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
采样速率:0.032 MHz最小供电电压:2.7 V
标称供电电压:3 V表面贴装:YES
温度等级:AUTOMOTIVE端子形式:NO LEAD
端子位置:QUADBase Number Matches:1

ADS131M04IRUKR 数据手册

 浏览型号ADS131M04IRUKR的Datasheet PDF文件第2页浏览型号ADS131M04IRUKR的Datasheet PDF文件第3页浏览型号ADS131M04IRUKR的Datasheet PDF文件第4页浏览型号ADS131M04IRUKR的Datasheet PDF文件第5页浏览型号ADS131M04IRUKR的Datasheet PDF文件第6页浏览型号ADS131M04IRUKR的Datasheet PDF文件第7页 
ADS131M04
SBAS890C – MARCH 2019 – REVISED JANUARY 2021  
ADS131M04 4-Channel, Simultaneously-Sampling, 24-Bit, Delta-Sigma ADC  
1 Features  
3 Description  
4 simultaneously sampling differential inputs  
Programmable data rate up to 32 kSPS  
Programmable gain up to 128  
The ADS131M04 is a four-channel, simultaneously-  
sampling, 24-bit, delta-sigma (ΔΣ), analog-to-digital  
converter (ADC) that offers wide dynamic range, low  
power, and energy-measurement-specific features,  
making the device an excellent fit for energy metering,  
power metrology, and circuit breaker applications. The  
ADC inputs can be directly interfaced to a resistor-  
divider network or a power transformer to measure  
voltage or to a current transformer, shunt, or a  
Rogowski coil to measure current.  
Noise performance:  
– 102-dB dynamic range at gain = 1, 4 kSPS  
– 80-dB dynamic range at gain = 64, 4 kSPS  
Total harmonic distortion: –100 dB  
High-impedance inputs for direct sensor  
connection:  
– 330-kΩ input impedance for gains of  
1, 2, and 4  
– 1-MΩ input impedance for gains of  
8, 16, 32, and 64  
Programmable channel-to-channel phase delay  
calibration:  
– 244-ns resolution, 8.192-MHz fCLKIN  
Current-detect mode allows for extremely low  
power tamper detection  
Fast startup: first data within 0.5 ms of supply  
ramp  
Integrated negative charge pump allows input  
signals below ground  
The individual ADC channels can be independently  
configured depending on the sensor input. A low-  
noise, programmable gain amplifier (PGA) provides  
gains ranging from 1 to 128 to amplify low-level  
signals. Additionally, this device integrates channel-to-  
channel phase calibration and offset and gain  
calibration registers to help remove signal-chain  
errors.  
A low-drift, 1.2-V reference is integrated into the  
device reducing printed circuit board (PCB) area.  
Cyclic redundancy check (CRC) options can be  
individually enabled on the data input, data output,  
and register map to ensure communication integrity.  
Crosstalk between channels: –120 dB  
Low-drift internal voltage reference  
Cyclic redundancy check (CRC) on  
communications and register map  
2.7-V to 3.6-V analog and digital supplies  
Low power consumption: 3.3 mW at 3-V AVDD  
and DVDD  
The complete analog front-end (AFE) is offered in a  
20-pin TSSOP or leadless 20-pin WQFN package and  
is specified over the industrial temperature range of  
–40°C to +125°C.  
Device Information (1)  
PART NUMBER  
PACKAGE  
TSSOP (20)  
WQFN (20)  
BODY SIZE (NOM)  
6.50 mm × 4.40 mm  
3.00 mm × 3.00 mm  
Packages: 20-pin TSSOP or 20-pin WQFN  
Operating temperature range: –40°C to +125°C  
ADS131M04  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
2 Applications  
Electricity meters: commercial and residential  
Circuit breakers  
Protection relays  
Power quality meters  
Battery test equipment  
AVDD  
DVDD  
1.2-V  
Reference  
AIN0P  
AIN0N  
+
Phase Shift  
Digital Filters  
&
Gain  
& Offset  
Calibration  
DS ADC  
DS ADC  
DS ADC  
DS ADC  
œ
SYNC / RESET  
AIN1P  
AIN1N  
+
Phase Shift  
Digital Filters  
&
Gain & Offset  
Calibration  
CS  
Battery management systems  
œ
SCLK  
Control &  
Serial Interface  
DIN  
DOUT  
DRDY  
AIN2P  
AIN2N  
+
Phase Shift  
Digital Filters  
&
Gain & Offset  
Calibration  
œ
Clock  
Generation  
AIN3P  
AIN3N  
+
CLKIN  
Phase Shift  
Digital Filters  
&
Gain &  
Calibration  
Offset  
œ
AGND  
DGND  
Simplified Block Diagram  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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