Datasheet > ADPD188GG-ACEZR7

ADPD188GG-ACEZR7

更新时间： 2024-01-19 11:06:19

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
61页	1068K
描述
Integrated Optical Module with Ambient Light Rejection and Two LEDs

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ADPD188GG-ACEZR7 数据手册

Integrated Optical Module with Ambient

Light Rejection and Two LEDs

Data Sheet

ADPD188GG

FEATURES

GENERAL DESCRIPTION

3.8 mm × 5.0 mm × 0.9 mm module with integrated optical

components

2 green LEDs, 2 PDs with IR cut filter

2 external sensor inputs

3, 370 mA LED drivers

20-bit burst accumulator enabling 20 bits per sample period

On-board sample to sample accumulator enabling up to

27 bits per data read

Custom optical package made to work under a glass window

Optimized SNR for signal limited cases

I²C or SPI communications

The ADPD188GG is a complete photometric system designed to

measure optical signals from ambient light and from synchronous

reflected light emitting diode (LED) pulses. Synchronous measure-

ment offers best-in-class rejection of ambient light interference,

both dc and ac. The module integrates a highly efficient photo-

metric front end, two LEDs, and two photodiode (PD). All of

these items are housed in a custom package that prevents light

from going directly from the LED to the photodiode without first

entering the subject.

The front end of the application specific integrated circuit (ASIC)

consists of a control block, a 14-bit analog-to-digital converter

(ADC) with a 20-bit burst accumulator, and three flexible,

independently configurable LED drivers. The control circuitry

includes flexible LED signaling and synchronous detection.

The analog front end (AFE) features best-in-class rejection of

signal offset and corruption due to modulated interference

commonly caused by ambient light. The data output and

functional configuration occur over a 1.8 V I²C interface or a

serial peripheral interface (SPI) port.

APPLICATIONS

Optical heart rate monitoring

Reflective PPG measurement

CNIBP measurement

FUNCTIONAL BLOCK DIAGRAM

VDD1

VDD2

PDC

ADPD188GG

PD1

EXT_IN1

CH1

BPF

±1 INTEGRATOR

TIA_VREF

VREF

PD2

1µF

EXT_IN2

CH2

TIA_VREF

PDC

PDET1

PD3

CH3

BPF

±1 INTEGRATOR

SCLK

MOSI

MISO

TIME SLOT A

TIA_VREF

DATA

PDET2

PD4

14-BIT

ADC

CH4

TIME SLOT B

DATA

SDA

SCL

VLED1

TIA_VREF

GREEN

GPIO0

GPIO1

DIGITAL

INTERFACE

AND

LED1/DNC

CONTROL

LED1 DRIVER

LED3 DRIVER

LED3

LED2

LED2 DRIVER

LGND

AGND

DGND

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN WHEN USING INTERNAL LEDs.

Figure 1.

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

No license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registeredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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