ADP3421
A resistor (RCLS) connected between the CLSET and ground
sets a current that is internally multiplied by a factor of three
and flows out of the CS– pin. The resistor RCL connected in
series with the CS– pin to the negative current sense point (i.e.,
the output voltage) sets the voltage that must be developed
across RCS to trip the current limit comparator. Once it is tripped,
the CS– current is scaled down by two-thirds, so the inductor
current must ramp down accordingly to reset the comparator.
Linear Regulator Soft-Start Timer
The soft-start timer circuit of the linear regulators is similar to
that of the core converter, and is used to control the ramp-up
time of the linear regulator output voltages. For maximum
flexibility in controlling the start-up sequence, the soft-start
function of the linear regulators was separated from that of the
core converter.
Level Translator
Core Converter Soft-Start Timer
The level translator converts any digital input signal to a user-
programmable voltage level. This can be used to translate an
IO-level signal (i.e., 1.5 V) into a CLK-level or VCC-level or
even 5 V-level signal. For example, the 1.5 V FERR# signal can
be converted to a 3.3 V level for the PII-X4 chipset. The output
signal is in phase with the input, and it is not necessary to have
a pull-up on the input signal. The ADP3421 provides pull-up
for the input signal to 1.5 V. The only practical restriction on
the input signal is that it must not prevent pull-up to 1.5 V. An
external pull-up resistor sets the output signal level. Throughput
time for the signal using a 150 Ω pull-up resistor is 5 ns (typ).
The soft-start function limits the ramp-up time of the core volt-
age in order to reduce the initial inrush current on the core
input voltage (battery) rail. The soft-start circuit consists of an
internal current source, an external soft-start timing capacitor,
an internal switch across the capacitor, and a comparator
monitoring the capacitor voltage.
The soft-start capacitor is held discharged when either the SD
signal is low or the device is in UVLO mode. As soon as SD is
set to high, and VCC and VIN rise above their respective UVLO
thresholds, the short across the external timing capacitor is
removed, and the internal soft-start current source begins to
charge the timing capacitor. During the charge of the soft-start
capacitor, the Power-Good signal is set to low. When the timing
capacitor voltage reaches an internally set soft-start termination
threshold, the core monitor window comparator output is
enabled, allowing the Power-Good status to be determined. If
the core voltage has already settled within the specified limits
the Power-Good signal goes high, otherwise it stays low. The
soft-start capacitor remains charged until either SD goes low,
or VCC or VIN drop below their respective UVLO thresholds.
When this occurs, an internal switch quickly discharges the
soft-start timing capacitor to prepare the IC for a new start-up
sequence.
APPLICATION INFORMATION
Overview—Combined ADP3421 and ADP3410 Power Con-
troller for PC Systems
The ADP3421 is a power controller that can provide a regula-
tion solution for all three power rails of an Intel Pentium II or
III processor. Together with the ADP3410 driver IC, these ICs
form an integral part of a PC system, featuring a high-speed
(<10 ns) level translator, interface with GCL and PII-X4
or other power management signals, and a power sequenced
switched 5 V rail. For high-slew-rate microprocessors, this
minimizes the total solution cost by allowing the quantity of
output capacitors to be minimized to the limit of what the buck
converter topology and the capacitor technology can allow.
Soft-Start Restart Lock In
Recommended Configuration
In the event that a UVLO event was not long enough to allow
the soft-start capacitors to discharge (e.g., a momentary power
glitch), the UVLO event is captured by a latch. The forced dis-
charge of the soft-start capacitors will continue until a lower
threshold is reached, at which time the converter will restart
with a fully controlled soft start.
The ADP3421 controls the regulation of the core voltage with-
out amplifiers in a unique ripple regulator control topology. In
a proprietary optimized compensation configuration offered
by Analog Devices, Inc., the inductor ripple current is kept at a
fixed programmable value while the output voltage is regulated
with fully programmable voltage positioning parameters, which
can be tuned to optimize the design for any particular CPU
regulation specifications. By fixing the ripple current, the fre-
quency variations associated with changes in output capacitance
and ESR for standard ripple regulators will not appear.
1.5 V I/O Voltage Regulator
Two pins control an external PNP, for example, transistor as
a linear regulator for a 1.5 V output. The IODRV pin directly
drives the base of the PNP with ≥10 mA to support an output
current as high as the PNP’s current gain and power dissipation
capability will allow. For example, with a high gain PNP transistor
such as the Zetex ZFT788B (SOT-223), the I/O linear regulator
is capable of delivering peak currents of greater than 2.5 A. The
1.5 V output is connected to the IOFB pin to provide feedback.
Accurate current sensing is needed to accomplish accurate out-
put voltage positioning, which, in turn, is required to allow the
minimum number of output capacitors to be used to contain
transients. A current-sense resistor is used between the inductor
and the output capacitors. To allow the control to operate with-
out amplifiers, the negative feedback signal is taken from the
inductor, or upstream, side of the current-sense resistor, and the
positive feedback signal is taken from the downstream side.
2.5 V CLK LDO Voltage Regulator
Two pins control an external PNP transistor as a linear regulator
for a 2.5 V output. The CLKDRV pin, for example, directly
drives the base of the PNP with ≥3 mA to support an output
current as high as the PNP’s current gain and power dissipation
capability will allow. For example, with a high gain PNP transis-
tor such as the Zetex ZFT788B (SOT-223), the CLK linear
regulator is capable of delivering peak currents of greater than
1.2 A. The 2.5 V output is connected to the CLKFB pin to
provide feedback.
Active voltage positioning, whose advantages are described later,
has two parameters that are separately controlled. The negative
feedback signal uses a resistor divider to ground into the RAMP
pin to create the precise offset voltage needed for voltage position-
ing. The positive feedback signal and the DAC’s VID-controlled
reference are summed into the REG pin through resistors to set
the desired voltage positioning gain. The proprietary optimal com-
pensation is a final parameter that must be tuned to ensure that
–8–
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