ADP3421
Microprocessors have the distinguishing characteristic of
creating extremely fast load transients from nearly zero to the
maximum load and vice versa. The advent of increasing power
management (used to interrupt the CPU processing) causes
these transients to occur with increasing frequency. Since it takes a
far longer time (typically on the order of several microseconds)
to ramp the inductor current up or down to the correct average
value after a load transient has occurred, the output capacitors
must supply or absorb the extra charge during that period of
time. This causes the output voltage to dip down or peak up.
The complete design procedure is supplied in a separate appli-
cation note from Analog Devices, Inc., entitled: DC-DC Power
Converter Design using the ADP3421 Controller.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
The ADP3421 is a high-speed controller capable of providing
a response time well under 100 ns. In order to avoid having the
ADP3421 respond to noise, the first step in achieving good noise
immunity is to follow the layout considerations.
In order to contain the output voltage within the specified limits
during load transients, with the minimum quantity of output
capacitors, the output voltage must be positioned as a function
of load, and it must be done so accurately. Therefore, current-
sensing with a discrete resistor (e.g., rather than using trace
resistance) is strongly recommended, as this will allow the number
of capacitors to be reduced toward the theoretical minimum—
which is nearly half as many as required for a standard fixed-
regulation technique. This is the key to minimizing the cost (and
also size) of the power converter.
In some layouts it may be necessary to supplement the ADP3421
control design with additional components designed to minimize
noise problems. For this purpose, some additional hysteresis can
be added around the core and current limit comparators. This
takes the form of adding a small capacitor (~1 pF) from OUT to
REG (for the main loop) and OUT to CS– (for current limit
loop), and providing some resistance for the capacitive hyster-
esis feedback to work against. For the current limit loop, this
register is already in the basic circuit. For the main loop, this
resistor must be added between the REG pin and the standard
feedback components. This provides a quick dynamic hysteresis
with a small time constant that is chosen only long enough to
ensure that the switching noise ringing through the circuit has
decayed by the time the dynamic hysteresis is substantially lost.
The voltage should be positioned (i.e., regulated) high at no
load and low at maximum load. This means that the power
supply will appear to have an initial offset and reduced load
regulation, because the output voltage will regulate higher than
nominal at no load and below nominal at maximum load. This
regulation technique positions the voltage in anticipation of a
load transient. At no load, the voltage is high, so when the load
transient strikes, the downward dip can be more easily contained
within the limits. Similarly at maximum load, the voltage is low,
so when the load transient strikes, the upward peak can be more
easily contained.
The following guidelines are recommended for optimal perfor-
mance of the ADP3421 and ADP3410 in a power converter.
The circuitry is considered in four parts: the power switching
circuitry, the output filter, the control circuitry, and the LDOs.
Placement Overview
1. For ideal component placement, the output filter capacitors
will divide the power switching circuitry from the control
section. As an approximate guideline, considered on a single-
sided PCB, the best layout would have components aligned
in the following order: ADP3410, MOSFETs and input
capacitor, output inductor, current-sense resistor, output
capacitors, control components, and ADP3421. Note that
the ADP3421 and ADP3410 are completely separated for
an ideal layout, which is only possible with a two-chip solu-
tion. This will minimize jitter in the control caused by having
the driver and MOSFETs close to the control and give
more freedom in the layout of the power switching circuitry.
Multiple MLC capacitors will always be needed on the output
across the CPU power pins to handle the high-frequency com-
ponent of the transient with minimized series inductance to and
through the bulk capacitors of the power converter’s output filter.
Although there are numerous trade-offs between size and cost of
various combinations of capacitor types for meeting a given
specification, the accurate voltage positioning provided by the
ADP3421 will allow the overall combination of capacitors to be
minimized.
A key requirement for optimizing the dynamic performance
of a power converter with accurate voltage positioning is to
apply “optimal compensation”—that is, the compensation that
creates a loop response that causes the output voltage to settle
immediately after a load transient, resulting in a “flat” transient
response. The ADP3421’s unique architecture is designed to
accommodate this ADI proprietary optimal compensation
technique in core dc-dc converters for Mobile CPUs. It is imple-
mented by creating the proper frequency response characteristic
at the summing junction of the output voltage and the DAC
voltage, which occurs at the REG pin.
2. Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding
it, is recommended. Two important reasons for this are:
improved current rating through the vias (if it is a current
path), and improved thermal performance—especially if the
vias extend to the opposite side of the PCB where a plane
can more readily transfer heat to air.
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