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ADP3421 PDF预览

ADP3421

更新时间: 2024-02-25 01:38:31
品牌 Logo 应用领域
亚德诺 - ADI 转换器DC-DC转换器控制器
页数 文件大小 规格书
12页 149K
描述
Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs

ADP3421 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:TSSOP,
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.22模拟集成电路 - 其他类型:SWITCHING CONTROLLER
最大输入电压:5 V最小输入电压:3 V
标称输入电压:3.3 VJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:9.7 mm
湿度敏感等级:3功能数量:1
端子数量:28最高工作温度:100 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
表面贴装:YES切换器配置:SINGLE
温度等级:OTHER端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

ADP3421 数据手册

 浏览型号ADP3421的Datasheet PDF文件第1页浏览型号ADP3421的Datasheet PDF文件第3页浏览型号ADP3421的Datasheet PDF文件第4页浏览型号ADP3421的Datasheet PDF文件第5页浏览型号ADP3421的Datasheet PDF文件第6页浏览型号ADP3421的Datasheet PDF文件第7页 
(0؇C Յ TA Յ 100؇C, VCC = 3.3 V, VSD = VCC, VULVO = 2.0 V, VCORE = VDAC, ROUT = 100  
k, COUT = 10 pF, CSSC = 1.8 nF, CSSL = 1.3 nF, CLTB = 1.5 nF, unless otherwise noted.)  
ADP3421–SPECIFICATIONS1  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
SUPPLY-UVLO-POWER GOOD  
Supply Current  
ICC(ON)  
ICC(UVLO)  
VCCH  
7
15  
350  
10  
mA  
µA  
µA  
V
VUVLO = 0.2 V  
VSD = 0 V, 3.0 V VCC 3.6 V  
VCC UVLO Threshold  
ICCH  
2.9  
VCCL  
2.7  
V
VCC UVLO Hysteresis  
Battery UVLO Threshold  
Battery UVLO Hysteresis  
VCCHYS  
VUVLOTH  
IUVLO  
20  
1.175  
–0.3  
0.6  
mV  
V
µA  
µA  
V
V
V
V
V
1.225  
1.0  
1.275  
+0.3  
1.4  
0.7 × VCC  
1.12 × VDAC  
1.10 × VDAC  
0.92 × VDAC  
0.90 × VDAC  
VCC  
VUVLO = 1.275 V  
V
UVLO = 1.175 V  
Shutdown Input Threshold  
Core Power Good Threshold  
VSDTH  
VCOREH(UP)  
VCOREH(DN)  
VCOREL(UP)  
3.0 V < VCC < 5.0 V  
0.925 V < VDAC < 2.000 V  
0.8  
1
1.10 × VDAC  
1.08 × VDAC  
0.90 × VDAC  
0.88 × VDAC  
0.95 × VCC  
0
2
1
2
VCOREL(DN)  
3
PWRGD Output Voltage  
VPWRGD  
VCORE = VDAC  
VCORE = 0.8 VDAC  
VUVLO = 0.2 V  
V
V
V
0.8  
0.4  
0
CORE CONVERTER SOFT-START TIMER  
Timing Charge Current  
Discharge Current  
Enable Threshold  
ISSC(UP)  
VSSC = 0 V  
VSSC = 1.7 V, VUVLO = 1.1 V  
–0.6  
0.3  
–1.0  
1.0  
150  
1.70  
–1.4  
µA  
mA  
mV  
V
ISSC(DN)  
4
VSSCEN  
400  
1.87  
Termination Threshold  
VSSCTH  
1.53  
VID DAC  
VID Input Threshold  
VID Input Pull-Up Current  
Nominal Output Voltage  
Output Voltage Accuracy  
Output Voltage Settling Time  
VVID0..4  
IVID0..4  
VDAC  
0.8  
10  
0.925  
–0.85  
0.7 × VCC  
40  
2.000  
0.85  
V
µA  
V
%
µs  
See VID Code Table I  
VDAC/VDAC  
5
tDACS  
35  
CORE COMPARATOR  
Input Offset Voltage  
Input Bias Current  
Hysteresis Current  
VCOREOS  
IREG  
IRAMP  
VREG = 1.3 V  
–3  
–2  
+3  
+2  
mV  
µA  
VREG = VRAMP = 1.3 V  
VCORE = VRAMP = 1.3 V  
VCS– = 1.30 V, VCS+ = 1.28 V  
V
V
REG = 1.28 V  
VHYS Open  
RVHYS = 170 kΩ  
RVHYS = 17 kΩ  
REG = 1.32 V  
R
–2  
–7  
–82  
+2  
–13  
–113  
µA  
µA  
µA  
–10  
–97  
RVHYS Open  
–2  
7
82  
1.53  
2.5  
0
+2  
13  
113  
1.87  
3.0  
0.4  
20  
µA  
µA  
µA  
V
V
V
ns  
ns  
ns  
RVHYS = 170 kΩ  
10  
97  
1.70  
RVHYS = 17 kΩ  
Hysteresis Setting Reference Voltage VVHYS  
Output Voltage  
VOUTH  
VOUTL  
tCOREPD  
VCC = 3.0 V  
VCC = 3.6 V  
TA = 25°C  
Propagation Delay Time6  
Rise and Fall Time6  
7
0°C TA 100°C  
30  
10  
8
tCORER  
,
7
8
tCOREF  
–2–  
REV. A  

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