Geyserville-Enabled DC-DC
a
Converter Controller for Mobile CPUs
ADP3421
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Meets Intel Mobile Voltage Positioning Requirements
Lowest Processor Dissipation for Longest Battery Life
Best Transient Containment
ADP3421
Minimum Number of Output Capacitors
System Power Management Compliant
Fast, Smooth, Output Transition During VID Code
Change
Programmable Current Limit
Power-Good
Integrated LDO Controllers for Clock and I/O Supplies
Programmable UVLO
Soft Start with Restart Lock-In
DACOUT
VID4
VID3
CLSET
CS+
CS–
VID DAC
VID2
VID1
CURRENT
LIMIT
COMPARATOR
VID0
VHYS
REG
EN
LTO
LTB
LTI
RAMP
LEVEL
TRANSLATOR
CORE
COMPARATOR
APPLICATIONS
OUT
Geyserville-Enabled Core DC-DC Converters
Fixed Voltage Mobile CPU Core DC-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
CORE CONTROLLER
CLKDRV
CLKFB
IODRV
CLOCK LDO
CONTROLLER
SSC
GENERAL DESCRIPTION
SSL
SOFT START
The ADP3421 is a hysteretic dc-dc buck converter controller
with two auxiliary linear regulator controllers. The ADP3421
provides a total power conversion control solution for a micro-
processor by delivering the core, I/O, and clock voltages. The
optimized low-voltage design is powered from the 3.3 V system
supply and draws only 10 µA maximum in shutdown. The main
output voltage is set by a 5-bit VID code. To accommodate the
transition time required by the newest processors for on-the-
fly VID changes, the ADP3421 features high-speed operation
to allow a minimized inductor size that results in the fastest change
of current to the output. To further allow for the minimum
number of output capacitors to be used, the ADP3421 features
active voltage positioning that can be optimally compensated
to ensure a superior load transient response. The main output
signal interfaces with the ADP3410 dual MOSFET driver,
which is optimized for high speed and high efficiency for driving
both the upper and lower (synchronous) MOSFETs of the
buck converter.
TIMER
AND
POWER GOOD
GENERATOR
I/O LDO
CONTROLLER
IOFB
BIAS AND
REFERENCE
CORE
BIAS EN
VIN/VCC
MONITOR AND
UVLO BIAS
REFERENCE
CONTROLLER
UVLO
VCC
GND
PWRGD
SD
REV. 0
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© Analog Devices, Inc., 1999